USB superspeed peripherals Forum Discussions

Hello

About FX3 C ++ Streamer;

Bulk transfer is understood as transfer in units of 1KB * 16Burst = 16KB.

For example, if I want to transfer data with Total Xfer length = 4MB using Streamer,

4MB / 16KB = 256

Therefore, it is understood that 1KB * 16Burst = 16KB unit is divided into 256 packets and 4MB is transferred. Is it correct recognition?

The specific questions are as follows.

Q1)

Is it correct to understand that the size of one packet is 16kB for Packets per Xfer in AN86947?

Q2)

What should I do if I want to flexibly change the settings of the Streamer application and check with a larger size (4MB or more / ex. 5MB,7MB)? Is there any way?

Best Regards

Arai

Hello,

I'd like to interpret the value epStatus (type of CyU3PUsbHostEpStatus_t ) which shows the transfer status.

However, so far I couldn't find any material which deals with it even on the FX3API guide and examples etc.

It would be great if someone can lead me to the relevant information.

Here are some of my logs on epStatus for example.

CyFxHostXferCb ep=0x81,epStatus=0x578081 CyFxHostXferCb ep=0x81,epStatus=0x1C78081 CyFxHostXferCb ep=0x81,epStatus=0x1 CyFxHostXferCb ep=0x81,epStatus=0x378081 CyFxHostXferCb ep=0x81,epStatus=0x1 CyFxHostXferCb ep=0x81,epStatus=0x578081 CyFxHostXferCb ep=0x81,epStatus=0x378081

Thanks for any comments.

Gents,

I am currently observing a curious behavior on a CX3 platform I have developed.
When users are trying to output frames with the following format 562x682xRAW8, frame size reported by the firmware (by summing DMA buffers size) is 384648 bytes which corresponds to a 564x682xRAW8 frame.
After some debug sessions it appears that, to work properly, line size has to be a multiple of 4 bytes otherwise some extra bytes are added at the end of each line.

As GPIF bus size is set to 16bits I was expecting line size to be a multiple of 2 bytes.

Is it a limitation of MIPI CSI-2 controller which has internal 32bit FIFO ?

Thanks for your support,

Stéphane

Hello Sir,

I implemented a composite device with two interfaces, one vendor specific and the other HID type. The HID interface uses a keyboard protocol.

The two interfaces (vendor and HID) work correctly, I have verified that the keyboard interface sends characters.

Now I would like the PC to be woken up by the FX3 when it goes into suspension, so I sampled an input that when it changes state generates a character towards the PC.

Unfortunately, the PC remains in suspension.

I also tried to use CyU3PUsbDoRemoteWakeup but I saw no improvement. The device is connected to USB3.

Do you have any advice on how to proceed?

Thanks in advance.

Niccolò

Hi,

we have an FX3 application connected via 32bit GPIF to an FPGA. The FX3 firmware is based on the Slave FIFO example with some small changes

(Endpoint configuration: 2 bulk endpoints, 1 int endpoint). During our extended tests that continuously transmit megabytes of data we occasionally

see problems on the USB3 link. In this case the FX3 does not accept any data from host but from FPGA side it looks like that the FIFOs are empty.

For analysis we read the phy and link errors from USB3 controller with CyU3PUsbGetErrorCounts. On failing hosts we can see that phy and link errors

increase. Furthermore, we read the CyU3PUsbEventLog and found that when one of these two events happen the link is blocked afterwards:

#define CYU3P_USB_LOG_USB_HP_TIMEOUT    (0xACu) /* USB 3.0 link header acknowledgement timeout. */

#define CYU3P_USB_LOG_USBSS_LNKFAIL        (0xADu) /* USB 3.0 link failure. */

What could be the reason for this kind of errors?

Is there any way to prevent the USB link from getting blocked when these events happen?

Is there any way to unlock the USB link after seeing these events?

Thanks,

Sven

Hi,

I am sending data to FX3 GPIF from FPGA in Async mode. Data bus width is 16 bit. I toggle the SLWR in 10MHz, push the data to socket 0, and I am able to read the data in USB PC side using a python script. When I change the speed to around 5MHz (means SLWR strobing not PCLK), I am not able to get any data out of USB. There is no changes in Flag A or B and slwr lines. But everything works as expected if the SLWR strobing happens at 10MHz.

I am using the SlaveFIFO2b example code in my FPGA. I was thinking that in Async mode, SLWR does not depend on speed of the clock. Please let me know what I am  missing here.

Cypress EZ USB Suite 提供的”MIPI Receiver configuration tool“，界面如下 ：

（1）PLL out clock/output pixel clock/CSI RX LP<->HS clock这是三个时钟之间有什么关系？比如CSI clock为200M（MIPI speed 400M），调节参数后PLL CLK/Pixel CLK/CSI RX LP<->HS clock应该是多少？

（2）为稳定收图像数据，其他参数调节需要注意什么？资料上没看到对应说明。

谢谢~

in our design, the CYUSB3065 is connect to FPGA with its I2C bus and the boot EEPROM is also on this I2C bus. We want the CYUSB3065 to boot from EEPROM. Is it possible to refresh a new firmware to the EEPROM by FPGA and then reset the CYUSB3065, thus booting from the EEPROM again with new firmware?

Do we have other ways to update EEPROM/SPI flash besides using USB(EZ-USB FX3 SDK)?

Thanks!

I'm trying to bring up OV2311 sensor using CYUSB3065.

I have the corresponding register settings for this sensor and set them accordingly in cyu3imagesensor.c file.

I need help in understanding and setting CX3 receiver configuration, Image sensor configuration (1600x1300 @30fps) and UVC descriptors for RAW10 output format

Please help and guide me in this regards.

Dears

USB Video Class 1_5的USB_Video_Payload_Frame_Based_1.5.pdf文档中定义了PAL 隔行的描述符，但是在AN75779的固件中没找到 bmInterlaceFlags 这个描述符，请问怎么修改成隔行呢？