USB superspeed peripherals Forum Discussions

Hello

"AN65974.zip"-> "FX3 Firmware"-> "Slave Fifo Sync"

→ There is the following description on line 892 of "cyfx slfifosync"

io_cfg.gpioSimpleEn [0] = 0;
io_cfg.gpioSimpleEn [1] = 0x08000000; / * GPIO 59 * /
io_cfg.gpioComplexEn [0] = 0;
io_cfg.gpioComplexEn [1] = 0;

Q1)
What will happen to the terminal state when all gpioSimpleEn are set to 0 (disabled)?
Q2-1) I think that the GPIO_SIMPLE register setting described on P.590 of FX3 TRM corresponds to the terminal setting in this case. Is this correct? if so,  would like to know the terminal status and necessary terminal processing in that case.
Q2-2) I think that DRIVE_HI_EN: 0 is a tri-state output if the initial value of the register. Is this correct?
Q2-3) Is it okay if external terminal processing is not required in the case of tri-state?

Please answer each  question mentioned above?

Best Regards

Arai

Hi,
Is there any example for using uart FX3 in half-duplex mode?
I am trying to use cyfxuartlpregmode example  for RS485 interface. so I had to add a gpio to control the this half duplex  communication. I set this gpio to True,  at first of while "in UartLpAppThread_Entry and set it false at the end of  that.
Also, I tested different places, but it doesn't work for me. 
Is there any clue for me to make it working?

I wrote another code without interrupt for send and receive only one byte. But I doesn't work . 
Is there any command to realize that UART received a whole byte completely?

for (;;)
{
       CyU3PGpioSetValue (gpio_half, CyFalse);
      // Receive 1 byte
       actualCount = CyU3PUartReceiveBytes(&rxTxByte, 1, &apiRetStatus);
 if (actualCount != 0 )
 {
       CyU3PGpioSetValue (gpio_half, CyTrue);
      //Send the byte

      CyU3PUartTransmitBytes (&rxTxByte, 1, &apiRetStatus); //actualCount =
      CyU3PGpioSetValue (gpio_half, CyFalse);
}

Thanks

I want to use Winbond's SPI Flash for FX3 SPI boot.

This KBA states that "it can be used if the command set is the same".

In the SPI I want to use, the instruction command DBh is block erase (64KB) instead of sector erase. Is it compatible even in this case (can I use this SPI?)

Thanks,
Tetsuo

Hi All! 

I'm trying to figure it out how make my own application by "Slave FIFO Interface" Example.

I use AN65974 document: "Designing with the EZ-USB FX3 Slave FIFO Interface".

I have "cyfxgpif2config.h" header generated by GPIFII Designer.

The AN65974 document  says  next: "This header file must be included in the firmware project" (Part 10 on page 23).

Also AN65974 says "The EZ-USB FX3 SDK includes a firmware example that integrates the Slave FIFO
interface".

I was trying to figure out how I can integrate this header into the firmware project by studying "SYNCHRONOUS SLAVE FIFO PROTOCOL EXAMPLE", but I couldn't figure out how to do it.

Help me please understend how I can integrate "cyfxgpif2config.h" header into the firmware project.

Hi Sir,

I saw a question about continue clock in the below path

https://community.cypress.com/t5/USB-Superspeed-Peripherals/Cypress-CX3-solution-Clock-Continuous-mode/m-p/54215

Q1: if my Serdes is non-continue clock, Can I use the same initial flow in non-continue clock ?  

Q2: if the answer of Q1 is No, just keep the initial flow from code Gen(Image Sensor Configuration )? Or Any other suggest?

Best Regards,

BenWang

At CX3, 

Sometimes (frequently) "CB Failure" is happened. 

After "CB Failure" was happend,  "ApInstop -> ApInStart"

(Now, system is working on 97fps, 1920x1200)

Logs (UART) are belows

==================================================

AplnStrt:SMState = 0x1
CB failure
AplnStop:SMState = 0x9
AppStart

AplnStrt:SMState = 0x2
CB failure
AplnStop:SMState = 0x7
AppStart

AplnStrt:SMState = 0x1
CB failure
AplnStop:SMState = 0x9
AppStart

AplnStrt:SMState = 0x2
CB failure
AplnStop:SMState = 0x5
AppStart

================================================

 Please, let me know how to fix it.

(I think when it was happened, system performance maybe is too low.) 

Hi, I knew the DR_GPIO action corresponds to Output Signal Setting. I’ve studied GPIFII_Designer_User_Guide, and have 2 questions for the GPIO polarity.

Q1:

What is “new value”? (or I can ignore the word)

Q2: According to the description for Output Signal Settings - Polarity:

Besides, DR_GPIO action CANNOT select the polarity in Assert mode.

Therefore, if Output Signal Settings - Polarity sets Active High, when DR_GPIO action is executed, the pin’s polarity will ALWAYS be high?

Any help will be highly appreciated!

Hi, I knew that the GPIF2: IN_DATA - Register corresponds to CyU3PGpifReadDataWords().

I’m more familiar with GPIF2: IN_DATA - Socket which links to DMA channel to receive data. After the data is full, it triggers callback function in FW.

It seems that the GPIF2: IN_DATA - Register don’t use the callback mechanism. Developer should call CyU3PGpifReadDataWords() in the FW manually.

Besides, I’ve studied the GPIF_EXAMPLE1.zip in third reply.

According to the GPIF_EXAMPLE1.zip - Slave Device, it seems that the FW calls CyU3PGpifReadDataWords() every second, which is ASYNC with state machine’s IN_DATA - Register.

Q1: If CyU3PGpifReadDataWords() is called earlier than GPIF2: IN_DATA – Register, CyU3PGpifReadDataWords() will return CY_U3P_ERROR_FAILURE or else?

Q2: If GPIF2: IN_DATA – Register is executed earlier than CyU3PGpifReadDataWords(), GPIF2: IN_DATA – Register  state will wait CyU3PGpifReadDataWords() before GPIF goes to next state?

Q3: what’s the different between the GPIF2: IN_DATA – Register and GPIF2: IN_DATA – Socket? Is the former slow?

Any help will be highly appreciated!

Hello,

During debugging a new camera design using the CX3, I began getting Abort Handler interrupts (in cyfxtx.c).  I have never seen these before and there's virtually no information about them in the CX3 or FX3 technical reference manual.

Can anyone explain what causes them?

Thanks,

Scott