USB superspeed peripherals Forum Discussions
Hi
I experience an FX3 EP_IN data transfer stop problem. Our design is based on the uvc_cdc example design.
UVC channel is auto_many_to_one DMA, the setting is:
dmaMultiConfig.size = 16384;
dmaMultiConfig.count = 4;
dmaMultiConfig.validSckCount = 2;
dmaMultiConfig.prodSckId [0] = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_0;
dmaMultiConfig.prodSckId [1] = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_1;
dmaMultiConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaMultiConfig.notification = CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;
dmaMultiConfig.consSckId [0] = (CyU3PDmaSocketId_t)(CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_SOCKET_UVC);
dmaMultiConfig.prodAvailCount = 0;
dmaMultiConfig.prodHeader = 0; /* 0 byte UVC header to be added. */
dmaMultiConfig.prodFooter = 0; /* 0 byte footer to compensate for the 12 byte header. */
dmaMultiConfig.consHeader = 0;
dmaMultiConfig.cb = CyFxUvcDmaCallback; /* use Capture mode's DMA callback */
apiRetStatus = CyU3PDmaMultiChannelCreate (&glChHandleUVCStream,
CY_U3P_DMA_TYPE_AUTO_MANY_TO_ONE,
&dmaMultiConfig);
CDC channel is manual DMA, the setting is:
/* Create a DMA_MANUAL channel between UART producer socket and USB consumer socket
* Use a smaller buffer size (32 bytes) to ensure that packets get filled in a short time.
*/
dmaCfg.size = 32;
dmaCfg.count = 32;
dmaCfg.prodSckId = (CyU3PDmaSocketId_t)(CY_U3P_LPP_SOCKET_UART_PROD);
dmaCfg.consSckId = (CyU3PDmaSocketId_t)(CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_SOCKET_CDC);
dmaCfg.notification = CY_U3P_DMA_CB_PROD_EVENT;
dmaCfg.cb = CyFxUART2USBDmaCallback;
apiRetStatus = CyU3PDmaChannelCreate (&glChHandleUarttoUsb,CY_U3P_DMA_TYPE_MANUAL, &dmaCfg);
Test setting is:
An app from host PC connect with FPGA through CDC channel. This app enable FPGA to generate UVC traffic, after this the app doing nothing, so there is no traffic flow on CDC channel.
Window "Camera" play video FPGA generated (sent to host PC through UVC channel). The rate is about 320M Bytes per second (90% of GPIF bus bandwidth)
The traffic stop is random, some time in a few minute, sometime a few hours, most time never happens. I am able to reproduce this problem by adding 4 hubs between host PC and device.
Most time when UVC traffic stop, CDC upstream traffic stop as well, CDC downstream traffic is still ok.
If I build FX3 firmware with SDK1.3.3, I can resume CDC upstream traffic by close and re-open host PC app(close and open uart port). UVC traffic can be recovered by changing video channel (in side FX3, uvc related endpiont and DMA channel will be deleted and re-created).
If I build FX3 firmware with SDK1.3.4, this problem will happen much much less often, but once happens, host PC apps freeze, I have to unplug USB cable to close apps, but in one time after about 20 seconds, CDC and UVC channel recovered by itself.
I used a USB analyser to capture traffic to and from FX3, there is no CRC error, the traffic stop is because FX3 send a NRDY transaction packet to host PC (there is no ERDY transaction packet send out by FX3 after NRDY)
Following is a screen shot of some captured data, there are about 30 to 50 unexpected transaction (in class view of usb analyzer) before NRDY, but they look the same as those good one.
Any one has any idea about this please give me a help, Thanks!
Show LessThe camera does not recognize it when I connect it to the USB port.
When I use the dmesg command to view the kernel log, I get the following message:
uvcvideo: No streaming interface found for terminal 4.
Can you tell me the solution?
Thank you.
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Hi,
I am sending stream data from the bulk endpoint to GPIF(BULK OUT). At the same time, I am sending/receiving data through UART (register mode) by Teraterm to FX3. Now I need to use Control Center(CC) to see whatever I got from Teraterm(stream data) or use CC to send TX data to Teraterm. I mean I want to change the firmware and maybe Visual C project somehow that Bulk OUT and UART traffic be able to send concurrently at the same time and can be accessible by Control Center.
I am doing some research to find a good way to transfer UART data to CC without any corruption on Bulk out data and vise versa. Based on KBA92475(of course, it is for BULH IN), Bulk transfers are found to corrupt control endpoint data, causing errors in the control pipe.
So my question is that is there any suggestion for this goal? which kind of endpoints would be more reliable and helpful to transfer from/to UART to CC to avoid any corruption when I am using BULK out endpoint at the same time? Is there any example to help me on that?
Thanks
Show LessHello Infineon Experts,
We use a CX3 and one or two related image sensors on our board, and we are facing a CY_U3P_ERROR_FAILURE value returned by the CyU3PMipicsiSetSensorControl() API. This behavior is random, but the error rate is over 20 %.
We probed the I2C bus and some other significant signals (CX3_RESET*, CX3_XRESET and CX3_XSHUTDOWN), to look what’s happen (see attached pictures):
- On successful execution, a first reading of Register 0x0012 (CY_U3P_MIPICSI_REG_GPIOIN) is done, bits [2:1] of this value are set to ‘1’ to drive High XRESET and XSHUTDOWN pins, the changed value is written to Register 0x0014 (CX3_CSI_SENSOR_SIG_VAL) and a second reading of Register 0x0012 is performed to be sure that Register 0x0014 is correctly written. So, reserved bits of Register 0x0014 are preserved as requested to section 1.10.7 of CX3 TRM.
- On fail execution, the second reading of register 0x0012 doesn’t match the writing to Register 0x0014 and the CyU3PMipicsiSetSensorControl() API returns CY_U3P_ERROR_FAILURE. The difference concerns the reserved bit 0.
Do you have an explanation for this error CY_U3P_ERROR_FAILURE?
For your information, both SDA and SCL signals are pulled high with 2kΩ resistors, and the I2C block is initialized (by calling CyU3PMipicsiInitializeI2c() API) before initializing the MIPI-CSI-2 block (i.e. before calling CyU3PMipicsiInit() API).
Best Regards,
Eric.
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Hi,
my firmware works well in 16bit mode. and now i want to change it to 32bit, GPIF has changed under the 16bit GPIF. and other changes in the project are all in those photos . but it seems can work, is there anything else need to change?
Thanks!
Show LessHello,
I developed to configure FPGA board using FX3.0 chip.
I used the C# application program developed with Form based project.
C# Form based APP program runs well.
I changed the C# Form based program to C# console based program.
My question is below...
In console based programs, how to operate two process sequentially runs.
1. download fx3.0 fw program 2. download fpga binary.
I did it.
But after first running...
"myDevice = usbDevices[0x04b4, 0x00F1] as CyUSBDevice;" is NULL...
second running is ok..
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Hello
I'm having some problems debugging with jlnk
1、How to achieve uart printing when using jlink for debugging
2、When debugging, the program does not stop when it encounters a breakpoint, and the breakpoint is invalid
I hope you can help me answer these two questions, thank you very much!
Hi
Is there any design examples or documentation on how to use EZ-USB® GX3 as USB port replicator.
For example, I want to connect remote USB device via ethernet cable (point to point) to PC that will think that a USB device was connected and will activate the USB driver for the remote device
Best Regards
Alex
Show LessHi
I encountered these problems while debugging the example USBBulkSourseSink in CX3 and my own configured CX3 UVC project using jlink .
1. When debugging the program, it does not stop at breakpoints.
2. When I step over CyU3PKernelEntry () API, it keeps debugging and does not stop.
I don't know if there is a problem with the debugging function or I have a debugging configuration error somewhere, because I have this problem with the example firmware debugging in CX3.
When I debug with USBBulkSourseSink it functions correctly, but there is no way to do single step debugging because the program doesn't stop every time it runs, so I have no way to debug at all。
My settings should be fine
When the debugging does not stop, I click terminate or suspend or disconnect to no avail, I can only disconnect jlink.
I hope someone can help me solve this problem, thank you very much!
Best Regard,
Yaqi
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Hi,
I want to transfer video data from FPGA to PC by using custom board FX3- CYUSB2014. Output data from FPGA : 640x480, 30 fps, 90 MHz clock, YUY2 format, 8 bit data bus connected with 2.0 USB cable to host PC. I edited AN75779 firmware but without success. I use VLC, USBVideoClassBulk works fine on my hardware. Is there anything am missing to change?
Tom
In cyfxuvcdsr.c file
/* Standard High Speed Configuration Descriptor */
/* Class specific Uncompressed VS Frame descriptor */
0x1E, /* Descriptor size */
0x24, /* Descriptor type*/
0x05, /* Subtype: uncompressed frame I/F */
0x01, /* Frame Descriptor Index */
0x01, /* Still image capture method 1 supported */
0x80,0x02, //z /* Width in pixel: 640 VGA */
0xE0,0x01, //z /* Height in pixel 480 VGA */
0x00,0x00,0xCA,0x08, //z /* Min bit rate bits/s. 640x480x30x16
0x00,0x00,0xCA,0x08, //z /* Max bit rate bits/s. Not specified, taken from MJPEG */
0x00,0x60,0x09,0x00, //z /* Maximum video or still frame size in bytes(Deprecated) */
0x15,0x16,0x05,0x00, //z /* Default Frame Interval 30 fps*/
0x01, /* Frame interval(Frame Rate) types: Only one frame interval supported */
in uvc.c file
uint8_t glProbeCtrl20[CY_FX_UVC_MAX_PROBE_SETTING] = {
0x00, 0x00, /* bmHint : no hit */
0x01, /* Use 1st Video format index */
0x01, /* Use 1st Video frame index */
0x15,0x16,0x05,0x00, //z /* Desired frame interval in the unit of 100ns: 30 fps */
0x00, 0x00, /* Key frame rate in key frame/video frame units: only applicable
to video streaming with adjustable compression parameters */
0x00, 0x00, /* PFrame rate in PFrame / key frame units: only applicable to
video streaming with adjustable compression parameters */
0x00, 0x00, /* Compression quality control: only applicable to video streaming
with adjustable compression parameters */
0x00, 0x00, /* Window size for average bit rate: only applicable to video
streaming with adjustable compression parameters */
0x00, 0x00, /* Internal video streaming i/f latency in ms */
0x00,0x60,0x09,0x00, //z /* Max video frame size in bytes */
0x00, 0x40, 0x00, 0x00, /* No. of bytes device can rx in single payload = 16 KB */
0x00,0x00,0x00,0x96, /* Max video frame size in bytes */
/* Configure the IO matrix for the device. */
io_cfg.isDQ32Bit = CyFalse;
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