USB superspeed peripherals Forum Discussions
Hi. I'm trying to replicate the original design https://community.infineon.com/t5/Knowledge-Base-Articles/EZ-USB-CX3-Interfacing-with-the-onsemi-AR0234CS-sensor-KBA236855/ta-p/402602 on your board (not the Denebola kit). I don't see any access to the sensor on the I2C bus. I started looking at the source code, I see the functions CyCx3ImageSensorInit(void), CyCx3ImageSensorSleep(void), CyCx3ImageSensorWakeup(void), but they are not called anywhere. What does it mean? I started adding CyCx3ImageSensorInit(); to the source code,- it works(there is activity on I2C) only up to the line CyU3PTimerCreate (&Cx3ResetTimer, cycx3appprogrestimer, 0x00, TIMER_PERIOD, 0, CYU3P_NO_ACTIVATE);. After this line,- does not work. The sensor connection is standard 4 lines, the generator on the sensor board is 27MGz. I attach a photo of the installation and terminal output. e-CamView sees the device, but cannot read frames.
Show LessHi,
On 16bit application + SPI, is it possible to use FV/LV on GPIO33 and 34?
If yes, on GPIFII interface i did not see the option to change the ctl pin to gpio.
Thanks
Hello
I'm experiencing some issues with FX3 when connected to an Asmedia USB 3.1 controller through AOC (Active Optical Cable). With this setup, the enumeration is never completed since after an LPM request the device receives a RESET USB command and starts back with enumeration process (below you can see the usb event log obtained through CyU3PUsbInitEventLog
).
USB3_PHY_ON: Indicates that the 3.0 PHY has been turned on.
LTSSM_CHG: Polling.LFPS
USBSS_CONNECT: Indicates that USB 3.0 Rx Termination has been detected.
LTSSM_CHG: Polling.RxEQ
LTSSM_CHG: Polling.Active
LTSSM_CHG: Polling.Configuration
LTSSM_CHG: U0
PORTCAP_DONE: Indicates that PORT_CAP handshake is completed.
PORTCFG_DONE: Indicates that PORT_CFG handshake is completed.
USBSS_SETCONF: Indicates that USB configuration has been selected.
LTSSM_CHG: U1
LTSSM_CHG: Recovery.Active
LTSSM_CHG: SS.Inactive.Quiet
USBSS_INACTIVE: USB 3.0 link inactive state.
LTSSM_CHG: Rx.Detect.Reset
USBSS_RESET: Indicates that a USB 3.0 reset (warm/hot) has happened.
LTSSM_CHG: Rx.Detect.Quiet
LTSSM_CHG: Rx.Detect.Quiet
LTSSM_CHG: Polling.LFPS
LTSSM_CHG: Polling.RxEQ
LTSSM_CHG: Polling.Active
LTSSM_CHG: Polling.Configuration
LTSSM_CHG: U0
PORTCAP_DONE: Indicates that PORT_CAP handshake is completed.
PORTCFG_DONE: Indicates that PORT_CFG handshake is completed.
USBSS_SETCONF: Indicates that USB configuration has been selected.
LTSSM_CHG: U1
LTSSM_CHG: Recovery.Active
LTSSM_CHG: SS.Inactive.Quiet
USBSS_INACTIVE: USB 3.0 link inactive state.
LTSSM_CHG: Rx.Detect.Reset
USBSS_RESET: Indicates that a USB 3.0 reset (warm/hot) has happened.
LTSSM_CHG: Rx.Detect.Quiet
LTSSM_CHG: Rx.Detect.Quiet
LTSSM_CHG: Polling.LFPS
LTSSM_CHG: Polling.RxEQ
LTSSM_CHG: Polling.Active
LTSSM_CHG: Polling.Configuration
LTSSM_CHG: U0
...
From the EZ-USB FX3 manual I've seen that an issue exists: "When FX3 device transitions from Low power U1 state to U0 state within 5 μs after entering U1 state, the device sometimes fails to transition back to U0 state, resulting in USB Reset."
The suggested workaround, disable LPM, was already present in my firmware, but the LPM is disabled only when high performance mode is selected (i.e. the device enables high bandwidth bulk/iso stream).
This issue seems to occur in early enumeration stage, when streams are not yet configured and no interrupt communication has yet happened. If I disable LPM at boot or I always force U0, the issue seems to be solved, but in this way I can't pass anymore USB3CV compliance tests and in general this seems to me a bad idea.
Moreover, this fix has a side effect when the camera enumerates as USB 2.0 device: the communication is slowed and I see several SUSPEND/RESUME events. This message flood is not present if I disable the BESL bit in the BOS USB 2.0 descriptor, but again, this involves another violation in USB3CV tests.
Is there a way to mitigate these issues without affecting the USB3CV tests?
Thanks
Show LessDear fx3 experts! I encountered a problem during development.
I used the 3014 chip, and the data stream was transmitted from FPGA to 3014 and then output through UVC.
When I use the Windows system, the video stream appears to be normal. But when I use the Mac system, the video stream will experience jitter. The video stream is good and bad at times, and this time is random.
I use manual DMA and print the values of prodCount and consCount in UVCAppServiceThread_Entry function. I found that when the video stream shakes, it does not enter the CyFxUVCDmaMultiCallback function, and the values of prodCount and consCount also increases(about 60).
The jitter phenomenon looks like that: the image in the upper part of the video stream has been updated, but the image in the lower part has not been updated, resulting in misalignment.
It looks like packet loss and something else, I don't really understand how to solve it.
Could someone give me some advice? Thanks.
Hi All,
I got a dll called CyUSBWrapper, I dont have the source code. but it looks something like this: (I used PeekDot to see the code). wanted to know if someone has the source code
Show Less
Hello,
I registered the falling edge interrupt of a gpio port on cyusb3014. The io port is the input port and the input value changes from 1 to 0 for a few seconds before changing back to 1. After receiving the interrupt, I read the level value of the io port. Theoretically, the level value of io is 0 when the interrupt is triggered, but I read the value of the io as 1 after the interrupt is triggered. May I ask if this is because my data value 0 is also ignored after the gpio interface triggers an interrupt?
Thank you.
Here is my code to simulate a serial port using the gpio port,
Please tell me what the problem might be, thank you!
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E8%B6%85%E9%AB%98%E9%80%9FUSB%E5%A4%96%E8%AE%BE/usb-suite-%E7%BC%96%E8%AF%91%E5%B7%A5%E7%A8%8B%E5%87%BA%E7%8E%B0%E9%97%AE%E9%A2%98/td-p/656578
Show LessDear all,
part of my product contains a UART <-> USB bridge, just like in the cyfxusbuart example.
I have it configured to DMA AUTO mode, but the thread loop have
const uint32_t uart_rx_enabled = UART->lpp_uart_config;
const uint32_t uart_rx_disabled = UART->lpp_uart_config & (~(CY_U3P_LPP_UART_RTS | CY_U3P_LPP_UART_RX_ENABLE));
while (true) {
if (!g_is_uart_app_active) {
CyU3PThreadSleep(SLEEP_TIME_50MS);
continue;
}
UART->lpp_uart_config = uart_rx_disabled;
CyU3PDmaChannelSetWrapUp(&g_dma_handle_uart2usb);
UART->lpp_uart_config = uart_rx_enabled;
CyU3PThreadSleep(SLEEP_TIME);
}
so that partially filled buffers are committed as well.
However, occasionally, random bytes are transmitted. Sometimes just a few, sometimes 64 bytes. I believe to have narrowed the issue down to the UART RX disabling, as I can provoke the issue by decreasing SLEEP_TIME (with 1 ms sleeps the issue happens at almost every transmission) and do not see the issue when omitting the UART->lpp_uart_config... part.
Unfortunately, this freezes the whole device after a random amount of time.
Interestingly, I see the same issue when configuring it in DMA Manual mode just as in the cyfxusbuart example.
How should I implement this?
Best regards,
Florian
We have created a FX3S driver for resell and it has been used successfully since 2022.
os : win 10 x64, win 10 x86; driver version : 1.2.3.20; chip : fx3s.
The device is now connected to a newly installed Windows 10 computer, and the (resell) driver is installed using the 'Device Manager' and 'Update driver' followed by 'Browse my computer for drivers'. The installation process reports:
The driver for this device has been blocked from starting because it is known to have problems with Windows. Contact the hardware vendor for a new driver. (Code 48)
How can this be fixed?
Show Less