USB superspeed peripherals Forum Discussions

Hi, Support Team 

          I have implemented a UVC appliaction on CX3 board.  There is a eeprom on my CX3 board, which stores some paras for calibrating . I would like to send it to PC via USB endpoints .  How to implement Endpoint Read/Write in an UVC application?

what should I do on CX3's firmware and how to do in my PC software? Should I  install a special driver for it?

Hi,
When my system reboots , it can't find FX3 in linux(I don't have this problem in windows).
I get "No device found", when I run cyusb_linux . (J4 is on). In linux, Fx3 needs to replug after reboot and then I can use it.
I attached the result of  lsusb -t  before repluging

Thanks

Hello,

I'd like to make a non-uvc project.

I referred to the below link then make a project successfully.

https://community.cypress.com/t5/Knowledge-Base-Articles/Steps-to-Setup-up-MIPI-CSI-Camera-Solution-...

However, I cannot build it with many errors even though I didn't add my own source yet.

I attached my project.

Please let me know what's the problem.

Regards,

Philip

Hi,

According to table 31 in AN76405 "EZ-USB® FX3™/FX3S™ Boot Options" the state of GPIO[17] a.k.a. CTL[0] is "Tristate" 

"while the bootloader is executing".

I have some questions related to that table.

Questions:

1) What is meant exactly by "while the bootloader is executing"? Does this table apply when you just plug the EZ-USB board into USB, before loading any firmware, so when the device enumerates as "Cypress FX3 USB Bootloader Device"?

2) The document  AN76405 states that the state of GPIO[17] a.k.a. CTL[0] is "Tristate". However, in the situation described under 1) I measure that GPIO[17] is HIGH (in my case 3.3V). Is this correct? My PMODE pins [2,1,0] are low,high,high (USB boot).

The question is relevant, because I use GPIO[17] as RESETN pin for an image sensor. When I first plug in the EZ-USB board into USB, I want GPIO[17] to be LOW to keep the image sensor in reset, before I load the actual firmware over USB. I tried a weak external pull down on GPIO[17] but that did not work, so it is definitely not in a TRISTATE condition as AN76405 suggests... 

I am trying to read from a Mfi chip through i2c using the FX3 SuperSpeed Explorer Kit. The transaction fails. I attached a scope capture showing a read of the mfi chip internal address 0x03. It looks like the chip is setting a short nak after the chip address (0x20). The FX3 i2c peripheral does not seem to care and the nak duration seems to be too short.

Do you have sample code that successfully reads or writes to a mfi chip?

Thanks.

Here is the thing that I 've bought an CYUSB3KIT-003,and I used it in slave fifo mode.  I used FLAGA and set it to gpio_21. As I understand it, gpio_21 is connected to the CTL_4 pin of the board so it should be logic 0 after the board is booted, however , its voltage was about 0.9V.

 How is it happen? 

Hello,

I'd like to test a custom module which is CSI-2 serial data output (MIPI 2lnae 960 Mbps/lane, D-PHY spec. ver. 1.2 compliant).

is it possible to test it using CX3?

If more information is needed to check it, let me know what it is.

Regards,

Philip

Dear Sirs,

Attached is part of my FX3 state machine when doing READing Data and the interface timing I suppose FX3 would be.

State machine will go from READ state to RD_WAIT state triggered by rfifo_empty(from external device:FPGA).

my question is :

If I just want to read 4 times, but state machine will go to RD_WAIT(slcs/slrd/sloe==HIGH) after it samples rfifo_empty==HIGH at positive edge of PCLK. If the interface timing is like what I draw, there will exist 5 read transfers.

How to avoid this situation? (Or maybe my assumption about interface timing is not correct)

Best regards,

james

Hello,

I would like to put the XRST pin in high with the following function: CyU3PMipicsiSetSensorControl (CY_U3P_CSI_IO_XRES, CyTrue); but when I call any function that contains Mipi I get the following error: 

Does anyone have any idea why? thank you