USB superspeed peripherals Forum Discussions

When we are using the FX3 in development everything works fine.

We have questions on switching over to our own VID/PID once we obtain a VID from USB-IF.

Currently we must program the FX3 with our APP image by using Cypress GUI “cyusb_linux” every time we power-up.

I see in the Cypress Library the routine to call that will do same and program our APP image into Fx3. But it doesn’t work.

Think won’t even compile? Once we program the efuse and have our won VID we will need to be able to program the FX3

By calling the library routine and not using the GUI cysb_linux, how do we do that?

When have own VID, does it get just programmed in when we load our own APP image?

What do we need to program the efuse? Can we do that with FX3 installed on our boards?

Do we need anything else to use the chip and ship it in systems?

Hi,

I'm working on a FX3 -> FPGA (Xilinx Artix 7) interface using the GPIFII interface.

I went through all the AN65974 document (a wonderfull piece:), but unfortunately, I was able to only make the Slave FIFO Write Sequence. I tried the loopback part without any success.

I had to modified it a bit since my system is only using 2 flags, therefore, I modified the GPIF to have current flag for A and B.

The write sequence went smooth and I was able to read data from the ControlCenter and retrieve a simple counter value. Very basic here.

I wanted to do the same with the read sequence but it never worked. I'm able to send data and see with Vivado debugger that the flag was raised. But no data get on the bus. Here is what I sent with the ControlCenter:

Once the data is sent, the flag is trigger in the FPGA and I get the following waves:

As you can see, the flaga was raised when I clicked on Transfer Data-Out but nothing appears on the bus. Note that the "q_data_in_use" is a clock signal that sample the value of the data bus (32 bits). I would expect to see my "ABCD_EF" appears at one time.

Also, since I only send 3 bytes, I would have expect the flaga to return to 0 very quicly. but as you can see in the waves, "slrd_n", "slrd_n" never go up and therefore, according to the timing diagram of the AN65974  document, I'm still in a burst read. Maybe I'm misunderstanding the flags here but I though that once my 3 bytes are read, the socket should be empty and the flag going down ('0'). Therefore, I could stop my read burst.

As of now, I decided to go to the very basic in order to debug what was going on. I did a new GPIF state machine to only support the read sequence:

SLWR&!SLCS&!SLRD&!SLOE  -> to go to read

SLRD|SLCS|SLOE -> return to IDLE

I wanted to avoid having a dead state so with this, there is only one possibiliy!

Note on my setup:
I'm using the AN65974 FX3 firmware with only the header file of the GPIFII which has changed as explained earlier.

I have also defined the "LOOPBACK_SHRT_ZLP" and undefined the "MANUAL".

I'm attaching the files of the FX3 firmware with the heater file of the GPIF.

I hope you can help me with that issue, it is really a big stopper for our development as we need to be able to both read and write to the host.

Thanks a lot in advance.

Marc-Olivier

Is it possible to use the SX3 "backwards" to can stream USB3 data to the SX3, then have it output video signals (RGB888, VSYNC, HSYNC, PCLK)? 

Alternatively, can I use the SX3 general purpose interface for this?  I am not sure I follow the data bus, but could I just use 24 of the 32 bits Slave FIFO and just write the video data out on that?

I know this is possible with the FX3, but I was wondering if there may be an easier way with the SX3 that avoids all the state machine GPIF II creation work, which I am trying to avoid.

Thanks.

Hi,
Our company want to resell FX3 driver(cyusb3.sys).
According to "Cypress CyUsb3.sys Programmer's Reference", Companies need to contact Cypress Technical Support and create a case with the below information to initiate the driver resell process.
1. Company details.
2. INF file with your devices VID/PIDs.

What should 1 and 2 do specifically?
I'm glad if you could tell me.

Thanks,

Hello

In conducting the USB compliance test,

Q1) Are there any registers that need to be checked to enable loopbacks and test patterns?

https://www.cypress.com/file/134661/download

Q2) There are two link test states (Loopback and Compliance mode), so I think there is a mode as FX3, but I don't know a concrete example of what to set and how.

Best Regards

Arai

Hello,

I have been trying to get an image stream running on a CX3 + OV5640 board without success.
The firmware contains UVC and CDC interface and the debug prints are sent correctly. 
I have other firmwares on which I'm able to get the image stream flowing without problem so I know there is no hardware issue on my board. 
From the debug logs, the size of the frames is 614400 and all of them seem to be correctly sent to the host. 

I spent couple of day trying to fix things and compare the working and non working versions that I have without being able to find the root cause.
At this point, it is not clear to me wether the problem is related to a misconfiguration of the sensor and Mipi interface or a problem with the firmware itself. 

I have attached the firmware, the debug prints from one session and the USB traces extracted via Wireshark. 

If anyone could have a quick look and give me hints, that would be really appreciated.
Thanks in advance for your help

Hi Team

Unfortunately, we have swapped a MIPI_CLK+ and MIPI_CLK-

Is there any possibility that Cx3 has an option that differential pair lines can be swapped internally? 

 Marked Nets are got swapped, 50th pin connected to MIPI_CLK+ and 52nd pin connected to MIPI_CLK-.

I'm currently looking into fitting the FX3 in our FPGA design. What we like to do is use the FX3 as "Async Slave FIFO" (fast ->DMA) for reading data from our FPGA. But we also like to use the FX3's I2C interface (slow -> non-DMA/register-mode) to write AND read to/from the FPGA (for registers etc.). We have a few questions about this scenario:

1) Can the "Async Slave FIFO" and I2C interface be used in the same (FX3) thread since it's mixing DMA reading and I2C reading (+writing)? Or perhaps do I need to use separate endpoints for DMA and non-DMA(I2C)?

2) Are there any examples for this scenario? We did find AN75779 but as far as we can tell the I2C interface in that example is only used for writing to the slave, not reading from it.

3) Is there anything else we need to take into account for this scenario?

Hi

Originally, these two fields are filled with 0, and it can work normally.
But now there is the issue of voice synchronization, It seems that these two fields must be filled.

I have read the explanation of UVC spec, but still don't understand

I want to understand how they calculate. Can you give me a tutorial or a simple example?

Do I need to update PTS field once per frame? And how is SCR calculated?

Thank you !