i was able to change the CY_FX_ISO_MAXPKT parameter.
when Running OUT Traffic (from the EP_OUT) from the streamer GUI, i was able to see in USB3 Trace that the Data len that my host is sending is actually the one that i defined in CY_FX_ISO_MAXPKT parameter.
my problem here is when i want to test the other way, IN_EP from the streamer GUI.
when choosing the IN_EP from the Streamer GUI and press on start, im able to see that there is traffic but in the USB3 Trace i see that the Data Len that the FX3 sending is always 0 no matter what CY_FX_ISO_MAXPKT is configured.
only when CY_FX_ISO_MAXPKT = 1024 i able to see that the FX3 is success to send ISOC Data Packet with Len = 1024 (verified it in the USB3 Trace).
is there something else that i need to configure? or maybe i miss something here?
more details (from the USBIsocSourceSink module) :
/* ISO Mult settings for SS and HS operation. */
#define CY_FX_ISO_PKTS (1)
/* Burst length in packets supported by the ISO endpoints, when operating in USB 3.0 mode. */
#define CY_FX_ISO_BURST (1)
/* Dma buffer size multiplier. As ISO endpoints will only transfer ISO_PKTS * ISO_BURST packets of data in*/
/* each interval, this can be set to 1 without any performance limitation. */
#define CY_FX_DMA_MULTIPLIER (1)
I am very new to the FX3 and I am trying to stream data from a 32 bit bus sampled at 10MHz to the computer. Data is sampled on the GPIF using two alternating threads. A program written on linux using libusb and cython simply reads 2MB of data (for now) and dumps it to the disk.
Currently, I have a testbench set up to generate a 16-bit binary counter to be sampled. However, looking at the dumped data returned, there are (seemingly random) gaps in the data where the counter will jump values. I cant seem to find any consistency as to where the data drops and how much will be lost.
Is there any way to figure out how to avoid packet loss?
I am currently using a USB2 High-Speed FTDI chip for USB-to-SPI conversion.
I am trying to get the lowest possible time to send multiple, small datagrams over SPI. I am not too concerned about the time to actually send the bits (so far at least, maybe withFX3 that's a new constraint!) which is only a handful of microseconds.
To test the speeds, I perform a loop to send 6 bytes back-to-back (Windows 10, 6-core Xeon, C#) 100 times then calculate the average time with the following psuedocode:
1. Start stopwatch
2. Chip select assertion
3. Read+Write 6 bytes over SPI bus at 10 MHz clock
4. Chip select de-assertion
5. Repeat #2 through #4 until 100 cycles are reached
6. Stop Stopwatch
7. Calculate average total time per SPI transaction (= Elapsed time of stopwatch divided by 100)
This yields about 700 microseconds per SPI transaction (on average) when the computer is doing nothing but running this loop, so it's probably a best-case situation.
Here's my questions:
1. If I use GPIO-controlled slave-selects with FX3, what is an estimate of the total cycle time I would see per SPI transaction (assume 6 bytes transfer, 10MHz clock)...can that 700 microseconds number drop substantially?
2. Would this be done with DMA mode or register mode? If the number could be dropped low enough I could test with some dummy writes and an oscilloscope with an FX3 eval to ballpark it.
This isn't a legally-binding number :).
I'm just trying to estimate if it would be worth testing something with an FX3 eval board for example. If that 700 microseconds could come down to below something like 150 microseconds I would consider spending time on it, but if you think it's not going to get that low I would pass and live with what I have.
I am facing an issue with SDK 1.3.4 while using multi thread. I have ported a project source to SDK 1.3.4 that I already used in SDK 1.3.1. I have not changed anything in my source code, I just build the source with 1.3.4.
In firmware we are just getting commands from HID call back, once I received command in HID call back I will set a event and in another thread I will wait for that event once I received the event I will perform my things. This simple concept is not working if I build my project in SDK 1.3.3 or SDK 1.3.4. Please help us to solve this issue at earliest.
Thanks and Regards,
Vignesh Kumar R.
I am writing firmware for the CX3 to interface a new sensor and am running into a confounding problem. My program behaves differently when I rearrange the order of functions in my C source code. This leads me to believe I have some memory corruption issues. I found the CyU3PMemCorruptionCheck() and CyU3PBufCorruptionCheck() functions in cyu3os.h and am trying to use them in my program. But when I do, the linker complains they are not defined. In what library are they defined?
Our Image Sensor has MIPI CSI-2® v3.0 (September 2019).
But CX3 has MIPI CSI-2 compliant (Version 1.01).
Does CX3 suitable for our design?Show Less
I have the following system: FPGA -> FX3(superSpeed explorer kit)->PC
I send counter from FPGA, but on pc i get shuffled data in multiples of packet size (1024)(1.png in attachments)
I try different parameters of DMA counts, DMA buffer size, but always the same
FX3 work on modified FIFO sync mode(from examples)
I'm not quite sure what other information to provide, so ask, I'll attachShow Less
I experience an FX3 EP_IN data transfer stop problem. Our design is based on the uvc_cdc example design.
UVC channel is auto_many_to_one DMA, the setting is:
dmaMultiConfig.size = 16384;
dmaMultiConfig.count = 4;
dmaMultiConfig.validSckCount = 2;
dmaMultiConfig.prodSckId  = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_0;
dmaMultiConfig.prodSckId  = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_1;
dmaMultiConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaMultiConfig.notification = CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;
dmaMultiConfig.consSckId  = (CyU3PDmaSocketId_t)(CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_SOCKET_UVC);
dmaMultiConfig.prodAvailCount = 0;
dmaMultiConfig.prodHeader = 0; /* 0 byte UVC header to be added. */
dmaMultiConfig.prodFooter = 0; /* 0 byte footer to compensate for the 12 byte header. */
dmaMultiConfig.consHeader = 0;
dmaMultiConfig.cb = CyFxUvcDmaCallback; /* use Capture mode's DMA callback */
apiRetStatus = CyU3PDmaMultiChannelCreate (&glChHandleUVCStream,
CDC channel is manual DMA, the setting is:
/* Create a DMA_MANUAL channel between UART producer socket and USB consumer socket
* Use a smaller buffer size (32 bytes) to ensure that packets get filled in a short time.
dmaCfg.size = 32;
dmaCfg.count = 32;
dmaCfg.prodSckId = (CyU3PDmaSocketId_t)(CY_U3P_LPP_SOCKET_UART_PROD);
dmaCfg.consSckId = (CyU3PDmaSocketId_t)(CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_SOCKET_CDC);
dmaCfg.notification = CY_U3P_DMA_CB_PROD_EVENT;
dmaCfg.cb = CyFxUART2USBDmaCallback;
apiRetStatus = CyU3PDmaChannelCreate (&glChHandleUarttoUsb,CY_U3P_DMA_TYPE_MANUAL, &dmaCfg);
Test setting is:
An app from host PC connect with FPGA through CDC channel. This app enable FPGA to generate UVC traffic, after this the app doing nothing, so there is no traffic flow on CDC channel.
Window "Camera" play video FPGA generated (sent to host PC through UVC channel). The rate is about 320M Bytes per second (90% of GPIF bus bandwidth)
The traffic stop is random, some time in a few minute, sometime a few hours, most time never happens. I am able to reproduce this problem by adding 4 hubs between host PC and device.
Most time when UVC traffic stop, CDC upstream traffic stop as well, CDC downstream traffic is still ok.
If I build FX3 firmware with SDK1.3.3, I can resume CDC upstream traffic by close and re-open host PC app(close and open uart port). UVC traffic can be recovered by changing video channel (in side FX3, uvc related endpiont and DMA channel will be deleted and re-created).
If I build FX3 firmware with SDK1.3.4, this problem will happen much much less often, but once happens, host PC apps freeze, I have to unplug USB cable to close apps, but in one time after about 20 seconds, CDC and UVC channel recovered by itself.
I used a USB analyser to capture traffic to and from FX3, there is no CRC error, the traffic stop is because FX3 send a NRDY transaction packet to host PC (there is no ERDY transaction packet send out by FX3 after NRDY)
Following is a screen shot of some captured data, there are about 30 to 50 unexpected transaction (in class view of usb analyzer) before NRDY, but they look the same as those good one.
Any one has any idea about this please give me a help, Thanks!Show Less
AMCAP application unable to display any data on its screen. On PC side we are able to see data through USB analyser but not on the AMCAP application.
Image sensor: AR1335
AR1335 configured with : RAW8 , 640*480 @ 2FPS and CSI clock-160MHz
CX3 MIPI Configurations :
INPUT video format : RAW8
OUTPUT video format : 24bit
640*480 @ 6FPS and CSI clock-160
CyU3PMipicsiDataFormat_t dataFormat : CY_U3P_CSI_DF_YUV422_8_2 (also tried CY_U3P_CSI_DF_RGB888 , CY_U3P_CSI_DF_RGB565_2 )
Number of bits per pixel: 16 (8 bit also tried )
Width in pixel: 320 (640 also tried)
0x59, 0x55, 0x59, 0x32, /*MEDIASUBTYPE_YUY2 GUID: 32595559-0000-0010-8000-00AA00389B71 */
0x00,0x00,0xe1,0x00, Min bit rate (bits/s):14745600=640*480*8*6
0x00,0x00,0xe1,0x00, Max bit rate (bits/s):14745600=640*480*8*6
0x00,0xb0,0x04,0x00, Maximum video or still frame size in bytes(Deprecated) 640*380
CX3- log :
TimeDiff = 10686 ms FPS = 2
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 31 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 32 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 33 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 34 Frm_Sz = 691200 B