USB superspeed peripherals Forum Discussions
Hi,
I've configured FLAGA to be Empty/Not Empty for Thread 0 during a read and Full/Not Full during a write. The timing diagrams in the "Designing with the EZ-USB FX3 Slave FIFO Interface" are a little confusing. Since the FlagA is shared, when is it asserted? For example, when a read cycle is initiated by asserting the address (2-bit in my case, "00"), the SLCS and the SLOE and the next cycle SLRD. Is the FLAG asserted after the SLRD goes active (low)? Also, the timing diagram shows the data valid 2 clock cycles after SLRD is this correct?
Thanks!
John
Show LessHi,
This is Zac from HPE.
We used CYUSB303X on one specific board for a while but now we need to migrate few power ICs to other vendors due to component shortage.
I notice that the CYUSB303X specified the voltage ramp up rate in the datasheet.
Our new power IC has similar 1.2V output ramp up rate which is close to CYUSB303X's: 50V/ms.
I'd like to know whether it's going to raise any concern or not.
Kindly advise.
Much appreciated.
Show LessMy reference is AN65974, in the writing sequence, I use Xferdata on PC and everything is fine until I open another application on PC, the fx3 board will stuck and have to be reset. I used the streamer application but didn't encounter such an issue. I found that the streamer application cpp uses BeginXferdata instead of Xferdata. In the API, it recommends Xferdata, is Xferdata cause the problem I encounter to?
Show LessHi
When I used the CYUSB3KIT-003 EZ-USB FX3, I got some weird condition.
The FLAGA became pull high after I send 5 times data and the EZ-USB FX3 became shutdown, also the PC side didn't recive any data from FX3 .(The FLAGA never pull low, the FX3 seems shutdown)
I already readed the application note AN65974. The FLAGA it means DMA Ready according the AN65974 said, also it just point out that when FLAGB pull low needs to stop send data.
So, how should I fixed this error?
B&R
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I'm studying CYUSB3014. I want to change the friendly name that shown by FX3 device.
I've tried to modify CyFxUSBManufactureDscr and CyFxUSBProductDscr, but it doesn't work. How can I do it?
Show LessHi Infineon support,
Today, based on the example code provide. firmware error message are send out to UART using CyU3PDebugPrint() function. Is there a way to read/send the error message through USB port to Control Center or Customer Application in the host PC?
Show LessWe've developed firmware for a Cypress FX3 that implements a single interface with 4 bulk endpoints. One of the endpoints is for commands, another for status, and the remaining two endpoints are for bulk data OUT and bulk data IN. The host application initiates a transfer by sending a command on OUT endpoint 1 and then reading a status response on IN endpoint 2. Bulk data (if part of the transaction) is then exchanged using OUT endpoint 3 and IN endpoint 4. Everything works as expected when the device enumerates as a USB 2.0 device. However, I'm having an issue with the status endpoint (IN endpoint 2) when in super speed mode.
The host side initiates a read of the status endpoint and then sends the command. The USB 3 packet analyzer (Ellisys USB Explorer EX350) shows that the device responds to the IN request with a NRDY packet. The command is then sent and received by the device, and by stepping through the firmware in the debugger I can see that the status response gets committed. However, the FX3 never responds with ERDY and per USB 3 specification, the host does not attempt to read the IN endpoint again.
I saw a couple of other posts about this that suggest that poor signal quality may be causing bus errors. I registered a callback for CYU3P_USBEP_SS_RESET_EVT but that event is never received.
If I re-arrange the order of operations on the PC side (send command and then issue status read) and put a delay between sending the command and then reading the status endpoint, the device does indeed respond with the expected status packet. However, this is because the device never entered a flow control state. It is unrealistic to expect the device to be able to deliver the data immediately each time the application asks for it. I see no way to avoid the device occasionally entering a flow control state where it needs to send ERDY after it previously sent NRDY. How do I get the device to place ERDY on the USB bus once data is committed to the endpoint?
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Hello,
We are facing an issue, that bulk IN data streaming hangs on CYUSB3KIT-001 DevKit (and other our devices base on FX3) connected to USB host controller ASM3142.
Issue was reproduced with FX3 sample FW "USBBulkSourceSink". After pressing "Start" in application "Streamer", device sends few USB packets and application hangs(sometimes causes BSOD on Windows). Bulk OUT works fine.
Issue has not been reproduces on other USB host controllers (such ASM2142, Intel, Fresco Logic..).
We have contacted ASMedia, they sent us latest FW, but issue still can be reproduced.
Has anyone faced the same issue? And how to fix/workaround it?
ASM3142 had been chosen due to Power Delivery and Type C connection.
Regards,
Sergey
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I'm creating a new question because it turned out that my old one didn't have the right answer after all, and it's locked now so I can't change it.
I have 4 endpoints that are set up as auto channels, with DMA notifications. They work great.
I tried to set up a fifth endpoint to do some logging from the DMA callback via a manual out endpoint. I've determined that it is seeing the new data every time a buffer is filled from one of those endpoints, and it's output works for 39 entries that I can see on the host, but then it stops working. Every time I try to call CyU3PDmaChannelGetBuffer after that, it fails with a CY_U3P_ERROR_MUTEX_FAILURE.
Show LessThanks for helping, but I encounter three issues while doing FPGA writing to slavefifo, the firmware is the Stream_in image file and the setting is default as it mentioned in AN65974.
1. After reading AN65974, I still can't understand the relationship between FLAGB and watermark, please explain to me.
2. FLAGB drop to low while FLAGA remaining high, what does it mean?
3. Although the issue above is not fixed, the USB host can still receive the data from FGPA after using Xferdata, but FLAGA and FLAGB will become low and not reset to high automatically, does that mean I have to reset the DMAchannel by using CyU3PDmaChannelReset?
The Appendix are the initial state and after writing data(Can't receive data this time).
Thanks a lot.
Regards,
Daniel
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