- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
ASUSTek Z87-K mainboard with Intel USB Host Controller
Windows 7 64Bit
CYUSB3014 SDK 1.3.3
Altera FPGA(EP4CE22) ==> CYUSB3014 ==> USB3.0 ==> Computer
FPGA write a low speed stream ( < 25Mbit/S ), CYUSB3014 use slfifosync example
transmit data, Streamer.exe receive data in Computer.
Under USB 3.0 mode, I change Packets per Xfer to 1 and set Xfers to Queue to 1.
Streamer.exe display Xfers failures every time ! there are more error at lower
speed.
But no error at high speed ( > 200MBit/S ).
At USB2.0 mode (use a usb 2.0 cable connect), every thing is OK.
Use slfifosync example in CYUSB3014 SDK 1.3.3.
Changes:
cyfxslfifosync.h
#define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT (0) ==> #define
CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT (1)
Use EZ USB Suite build it and use CyControl.exe write to CYUSB3014 RAM .
VHDL in FPGA:
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY USBData IS
PORT(
NRST : IN STD_LOGIC;
SYSCLK : IN STD_LOGIC;
USB_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
USB_FLGA : IN STD_LOGIC;
USB_FLGB : IN STD_LOGIC;
USB_INT : IN STD_LOGIC;
USB_CS : OUT STD_LOGIC;
USB_WR : OUT STD_LOGIC;
USB_RD : OUT STD_LOGIC;
USB_OE : OUT STD_LOGIC;
USB_A0 : OUT STD_LOGIC;
USB_A1 : OUT STD_LOGIC;
USB_PKT : OUT STD_LOGIC
);
END USBData;
ARCHITECTURE Bodys OF USBData IS
CONSTANT BURSTSIZE : INTEGER := 128;--USB BURST LENGTH: 16*4=64 BYTE
128*4=512 BYTE 256*4=1024 BYTE
CONSTANT IDLETICKS : INTEGER := 50000;
SIGNAL sBit : STD_LOGIC;
SIGNAL nDataCount : INTEGER:= 0;
SIGNAL nIdleCount : INTEGER:= 0;
SIGNAL nState : NATURAL RANGE 0 TO 3;
BEGIN
PROCESS(NRST, SYSCLK)
BEGIN
IF NRST = '0' THEN
USB_DQ <= (OTHERS=>'Z');
USB_CS <= '1';
USB_WR <= '1';
USB_RD <= '1';
USB_OE <= '1';
USB_A0 <= '0';
USB_A1 <= '0';
USB_PKT <= '1';
sBit <= '0';
nDataCount <= 0;
nIdleCount <= 0;
nState <= 0;
ELSE
IF RISING_EDGE(SYSCLK) THEN
USB_DQ <= (OTHERS=>'Z');
USB_CS <= '0';
USB_WR <= '1';
USB_RD <= '1';
USB_OE <= '1';
USB_A0 <= '0';
USB_A1 <= '0';
USB_PKT <= '1';
CASE nState IS
WHEN 0 =>
nIdleCount <= nIdleCount + 1;
IF nIdleCount = IDLETICKS THEN
nIdleCount <= 0;
nDataCount <= 0;
nState <= 1;
END IF;
WHEN 1 =>
IF USB_FLGB = '1' THEN
IF nDataCount < BURSTSIZE THEN
nDataCount <= nDataCount + 1;
sBit <= NOT sBit;
USB_DQ <= (OTHERS=>sBit);
USB_WR <= '0';
ELSE
nState <= 0;
END IF;
ELSE
nState <= 0;
END IF;
WHEN OTHERS =>
nState <= 0;
END CASE;
END IF;
END IF;
END PROCESS;
END Bodys;
----------------------------------------------------------------
The VHDL codes write to CYUSB3014 with 0xFFFFFFFF00000000FFFFFFFF00000000...
Burst length is 512 bytes,
Idle ticks set to 10000,
The clock from FPGA'pll is 90MHz,
I change IDLETICKS to any value to check speed.
If IDLETICKS = 10000, bit stream speed is (128*32)/((129+10000)/90000000) =
36.4M bit/S
If IDLETICKS = 50000, bit stream speed is (128*32)/((129+50000)/90000000) =
7.35M bit/S
At USB 3.0 mode, the lower the rate, the more errors.
What can i do on this problem ?