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USB Superspeed Peripherals

doch_3739346
Contributor

Hi,

RD_START is the START State for read command.

pastedImage_0.png

SRAM_READ_COMMAND, CyU3PGpifSMSwitch start state changed to RD_START.

pastedImage_1.png

Linux application read from endpoint 0x81.

r = cyusb_bulk_transfer(h1, 0x81, buf, 64, &transferred, timeout * 1000);

But never detect transaction over GPIF to FPGA interface. How to make it work?

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1 Solution
SrinathS_16
Moderator
Moderator

Hello,

- Have you passed the vendor command with the request 0xBB before reading data from the FX3?

- Is there any error code returned on the cyusb_bulk_transfer() function call? If yes, please mention the same.

- Before using the cyusb_bulk_transfer() function call, have you obtained the handle to the device, checked if the kernel driver is active and claimed the interface using the cyusb_gethandle(), cyusb_kernel_driver_active() and cyusb_claim_interface() function calls respectively.

EDIT: For reading data from the FPGA over to the USB interface, the slave interface must be configured and the SLWR#, ADR[1:0], PCLK must be driven by the FPGA(master). If there is no signalling on the GPIF II interface, the FPGA code has to be checked. The cyusb_bulk_transfer() function call on the IN endpoint reads the data that is present in the FX3 FIFO buffer.

Best regards,

Srinath S

View solution in original post

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3 Replies
SrinathS_16
Moderator
Moderator

Hello,

- Have you passed the vendor command with the request 0xBB before reading data from the FX3?

- Is there any error code returned on the cyusb_bulk_transfer() function call? If yes, please mention the same.

- Before using the cyusb_bulk_transfer() function call, have you obtained the handle to the device, checked if the kernel driver is active and claimed the interface using the cyusb_gethandle(), cyusb_kernel_driver_active() and cyusb_claim_interface() function calls respectively.

EDIT: For reading data from the FPGA over to the USB interface, the slave interface must be configured and the SLWR#, ADR[1:0], PCLK must be driven by the FPGA(master). If there is no signalling on the GPIF II interface, the FPGA code has to be checked. The cyusb_bulk_transfer() function call on the IN endpoint reads the data that is present in the FX3 FIFO buffer.

Best regards,

Srinath S

View solution in original post

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doch_3739346
Contributor

Hi Srinath,

1. Could you give me details about "passed the vendor command with the request 0xBB before reading data from the FX3".

2. There is no error code returned, it's locking up.

3. Before cyusb_bulk_transfer(), I've run cyusb_open(),  cyusb_gethandle(), cyusb_kernel_driver_active(), cyusb_claim_interface(), from return value, all functions run sucessfully as below.

root@ensigma-lab:/user/dgc/shared/USB/FX3_SDK_1.3.4_Linux/cyusb_linux_1.0.5/src# ./08_cybulk

cyusb_open return: r = 1

cyusb_gethandle return: h1 = 4b4

cypress chipset detected

Successfully claimed interface

4. I've done an experiment, set GPIF RD_START as FSM reset state. After reset, I can see FX3 starts reading data from FPGA. Basically FPGA is working fine, if FX3 can start reading process.

Now need to figure out why RD_START state is never reached.

pastedImage_0.png

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doch_3739346
Contributor

Need to use below function to start RD_START.

r = cyusb_control_transfer(h1, 0x40, 0xBB, 0x0000, 0x0000, buf, 16, timeout * 1000);

Details can be found in Why SRAM_READ_COMMAND is never run?

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