When watervalue was set as 6,the host transfer 2160KB+4B,can i received all the data at the fpga ?

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yxx0803
Level 3
Level 3
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Hello,

From KBA https://community.cypress.com/t5/USB-Superspeed-Peripherals/X-gt-16KB-let-Y-X-16-KB-Y-lt-16KB-and-X-...  I have asked you how to transfer 2160KB+4B from PC to FPGA.Some settings in my design as follows:

DMA buffer:       16KB(size)X 2(number)

In my firmware:CyU3PGpifSocketConfigure (3,CY_U3P_PIB_SOCKET_3,6,CyFalse,1);   

watervalue:6

databus width:32

flagc:Thread3_DMA_Ready

flagd:Thread3_DMA_WaterMark

 

As  that KBA mentioned:The sum 2160KB + 4B is not divisible by 16KB. This means that the last DMA buffer will have 4B data and will not be committed to the FPGA side.

Now, I have transfered 2160KB+4B successfully at host side becase the function named xferdata returned true.

And I want to know when  2160KB+4B transfered successfully, the last 4B data will be committed to the FPGA side,flagd can work well or not?    Flagc will be '1',flagd will be 1?

Best Regards,
Jack chen
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1 Solution
AliAsgar
Moderator
Moderator
Moderator
1000 replies posted 250 solutions authored 750 replies posted

Hello,

The number of data words available for reading after the clock edge at which the partial flag is sampled asserted = watermark x (32/bus width) – 1.
Watermark value of 6 indicates reading of 5*4B = 20B more of data from a buffer. But the last buffer contains just 4B. So below two steps could be tried :

1. Change the watermark value to 1.

2. Keep the watermark value as 6 and add dummy data to make the total size as 2160KB+20B. Discard the dummy data at the FPGA side.

Please tell us the results after performing the above tests.

Best Regards,
AliAsgar

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3 Replies
AliAsgar
Moderator
Moderator
Moderator
1000 replies posted 250 solutions authored 750 replies posted

Hello,

The number of data words available for reading after the clock edge at which the partial flag is sampled asserted = watermark x (32/bus width) – 1.
Watermark value of 6 indicates reading of 5*4B = 20B more of data from a buffer. But the last buffer contains just 4B. So below two steps could be tried :

1. Change the watermark value to 1.

2. Keep the watermark value as 6 and add dummy data to make the total size as 2160KB+20B. Discard the dummy data at the FPGA side.

Please tell us the results after performing the above tests.

Best Regards,
AliAsgar

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yxx0803
Level 3
Level 3
50 sign-ins 25 replies posted 25 sign-ins

Thanks a lot!got it.

Best Regards,
Jack chen
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AliAsgar
Moderator
Moderator
Moderator
1000 replies posted 250 solutions authored 750 replies posted

Hi,

Could you confirm which of the above two steps worked for your case?

Best Regards,
AliAsgar

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