UvcHandleDmaReset repeated

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LuckyLuo
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Dear sir ,

In my FX3 case,  why the UvcHandleDmaReset repeated after   OBS  app  invoke usb3 device enumerated as  FX3 IS CAM RDK  .   The FX3 connected to the FPGA chip which burned  in color bar bit file. 

fc8dcd84683fa904a619a4a53c0e670.png

The waveform   showed below, 

4f8327aad2c2ceed76063421667e96c.png

Thanks and BR

LuckyLuo

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JayakrishnaT_76
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Editted

Hello,

Please let me know if you were able to configure the FPGA correctly based on the interface timings provided in AN65974 to perform the data transfers correctly.

Update from customer:

The PCB on which the tests were done was broken when it was cut for probing signals. The customer was able to successfully transfer data using another board which was not broken and also by following the interface timings mentioned in AN65974 correctly.

Best Regards,
Jayakrishna

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JayakrishnaT_76
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Hello,

As per our understanding, initially you were able to stream some amount of data sent from FPGA to host through FX3. But, at a point of time, streaming stopped. Please confirm if our understanding is correct or not.

As you might be knowing, this issue is caused because of the expiry of a timer implemented in the firmware. The timer expires after a predetermined time  (which is set in firmware) if FX3 does not receive data from FPGA. Please try to increase the variable glFrameTimerPeriod from 200 to 500 and let us know if you find any improvements. 

Also, please share the complete UART debug logs and traces so that we can understand the problem better.

Best Regards,
Jayakrishna
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LuckyLuo
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Dear Jayakrishna,Sorry to relpy so lately  as i review the fpga code these days.

I try to increase  glFrameTimerPeriod  = 500 ,but nothing change.

b06c704a7366baae5e0954265e00cad.png

01c8d6422f8e8c84e2bfde1814b09ad.png

The complete UART debug logs  has been attched.

Best regards,

Lucky Luo

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JayakrishnaT_76
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Hello,

Thanks for sharing the complete UART debug logs. But, we did not find the complete traces (logic analyzer probed) that was also requested in my previous response. Please share the traces also so that we can understand the issue more. 
Also, can you please try the test on multiple devices and let us know if all of them has the same issue?

Best Regards,
Jayakrishna
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LuckyLuo
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Dear Jayakrishna,  Thanks for your reply.

In the inital state, using CTRL3  Fall_edge trig , logic analyzer capture the waveform show as below

e73afc1f314850729313ff379d09fa2.png

enlarge the part for more detail 

cf35b6dc216dfb0a6f01914ba19efe6.png

Then start up the OBS,  using SLOE_reset_CTL2  falling edge trig, can get waveform as blow

11b343f67da85520389ba02951da278.png

Enlarge the first falling edge of N0.5 channel

82c6eb02d555f35922754f9cd6ccbff.png

 Enlarge the second falling edge of N0.5 channel

8954bd0c258c9012ed89a38e6317b80.png

After the second falling edge of N0.5 channel,,the waveform is repeated.

I thinks the FX3 device has been in  CyFx3UvcHandleDmaReset function, which call CyFx3UvcAppStart and CyFx3UvcAppStop repeated.

ea6f5232d67e982ec9072fe9dbf0a9d.png

I test on the other devices which has the same model pcba, has the same issue.

Best Regards,
Lucky Luo

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JayakrishnaT_76
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Hello Lucky Luo,

Can you please share the complete trace file with us instead of sharing snapshots? This will be more easy for us to check and does not require switching between the snapshots. If it is not possible to attach the captured trace file in the community, then please share it to my email ID given below:

email ID: Jayakrishna.TN@infineon.com

Please capture the FLAG A signal also in addition to the ones probed and shared in the snapshot. Also, please capture the UART debug logs simultaneously while capturing the traces of these signals and also share the same with us for checking.

In addition to this, please let us know when will the FPGA send out image data to FX3? As per my understanding, it happens when both SLRD and SLOE are high (both of which are driven by FX3). Please correct me if my understanding is wrong.

Best Regards,
Jayakrishna
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LuckyLuo
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Dear Jayakrishna,

The complete trace file has been sent to you with your email ID.

In the FPGA code , the FLAG A signal  is no use. Only FLAG B  was used. It is right that FPGA stream out data to FX3 when both SLRD and SLOE are high.

612f42bc798069ad2905656ebb50200.png

Best Regards

Lucky Luo

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JayakrishnaT_76
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Hello,

I got only the UART logs via email. I did not receive the traces of signals probed using logic analyzer.

Please probe PCLK also along with other signals using the logic analyzer.  This is to understand for how many clock  cycles were the signals driven by the FPGA. After probing, instead of sharing snapshots, please share the complete file generated by the software so that we can zoom in or zoom out depending on the requirement. 

I understand that Flag_A is not used by FPGA. The state of Flag_B should be used by FPGA to understand if a DMA buffer is available on FX3.  Please correct me if my understanding is wrong. In this case, how is the transmission of data terminated at the FPGA side? Is it done by checking the state of Flag_B?

Best Regards,
Jayakrishna
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LuckyLuo
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Dear Jayakrishna, I am sorry that

I am sorry that  i cannot export the capture file  as  i use the very early version of the logic analyzer software. And i try to install the latest version software ,but  my pc cannot  emunurate the logic analyze,  nor  the other notebook. So ,i think i need to buy a high quality one.  As the same reason,i am sorry that  this cheaper device cannot capurte  Pclk as it will make the other channel  interference.  Maybe the high quailty logic analyze can  filter the noise.

Best Regards,

Lucky Luo

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JayakrishnaT_76
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Hello Lucky Luo,

Please provide your comment on the following question asked in my previous response

"I understand that Flag_A is not used by FPGA. The state of Flag_B should be used by FPGA to understand if a DMA buffer is available on FX3.  Please correct me if my understanding is wrong. In this case, how is the transmission of data terminated at the FPGA side? Is it done by checking the state of Flag_B?"

As mentioned before, the firmware makes use of a timer. This timer on expiry will trigger Appstop() and Appstart(). As seen from the logic analyzer captures, the data is not received properly from FPGA. This causes the timer to expire and this in turn triggers Appstop() and Appstart() repeatedly. There is a provision to disable this timer in firmware. This can be done by commenting the following line in cyfx3_uvc.h file:

#define FRAME_TIMER_ENABLE

Along with this, the APIs CyU3PTimerModify() and CyU3PTimerStart() used in CyFx3ApplnDmaCallback() and CyU3PTimerStop() used in CyFx3UvcAppUSBSetupCB() should also be commented out to build the project successfully for testing. Please try this and let us know if you are seeing the repeated sequence of Appstop() and Appstart() again.

Best Regards,
Jayakrishna
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LuckyLuo
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Hello Jayakrishna, 

At first, I am sorry i make a messy using no use instead not use. It is true that Flag_A is not used by FPGA. You are so smart to correct my type error.

Further, I checked the FPGA code, i found only using FLag_B(DMA Ready flag) to start sending data to FX3 . Then, FPGA  terminated  as soon as   2 bytes data tranfer finished .  It will monitor  the  FLag_B falling edge continually .

Subsequently, I try to disable FRAME_TIMER  the repeated sequence disappear.  But there is no data tranfer to usb host.  It seem stucking  in someway.  I send  the uart log and usb trace to your email already. Hope you can  receive it.

Best Regards,
Lucky Luo

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JayakrishnaT_76
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Hello,

Thank you for sharing the UART debug logs with us. But, I found that the wireshark traces were shared as .txt file. Please share it as .pcap file so that it is easy for us to review. If the file size is large, then please compress it and share it with us.

From the UART debug logs after disabling the FRAME_TIMER, I understood that there is no transfer to USB host. This is because FX3 is not receiving the data from the FPGA properly. This was confirmed from the ART debug logs shared with me over email.

Can you please elaborate the working of FPGA code so that we can debug the issue quicker? This is because your last post seems to be confusing. As per your last post, I understood that FPGA waits for FLAG_B from FX3 to start data transfer. Once FLAG_B is high, FPGA will send data to FX3. Once FPGA transferred 2 bytes of data to FX3, the FPGA will stop the data transfer. Please let us know if our understanding is correct or not.

If our understanding is correct, then please let us know what exactly was meant by the following line in your last reply:

 "It will monitor  the  FLag_B falling edge continually".

Best Regards,
Jayakrishna
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LuckyLuo
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Dear Jayakrishna,Thanks for you reply !

I would like to answer your query in the last email before we connect.  Once FLAG_B is high, FPGA will  send data to FX3.   the FLag_B is always mointed  with the falling edge   untill  timer  overflow.

Best Regards,
Lucky Luo

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JayakrishnaT_76
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Moderator
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First question asked 1000 replies posted 750 replies posted

Editted

Hello,

Please let me know if you were able to configure the FPGA correctly based on the interface timings provided in AN65974 to perform the data transfers correctly.

Update from customer:

The PCB on which the tests were done was broken when it was cut for probing signals. The customer was able to successfully transfer data using another board which was not broken and also by following the interface timings mentioned in AN65974 correctly.

Best Regards,
Jayakrishna
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