We are using Cypress EZUSB (CYUSB3065) for our product.
In our design, we are using SPI boot (0F1) and then reusing the Pmode pins as GPIOs.
My questions are:
1. After a watchdog reset, will the Pmode pins get sampled again and firmware reloaded from SPI flash.
2. If so, will the settings performed by the CX3 firmware on GPIO-32 (SET TO 1) affect the Pmode boot latching.
Watchdog timer in FX3 can be used to reset the CPU. CPU reset will reset the Program Counter. In this case, firmware reload is not required, meaning PMODE pins won't be sampled again.
If firmware is not loaded, how will the initialized data section of the firmware get reset. Would it continue to be stale. If the reset occurred due to bad data, then this could send the cx3 in infinite wdog reset loop ? how to avoid this.