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USB Superspeed Peripherals

New Contributor II

Background: I'm designing an interface where I paired an FPGA with the FX3. I opted to use the "Synchronous Slave FIFO Interface" to interface with the FPGA. The FPGA is paired with 512MB buffer memory. The FPGA should only send streaming (bulk) to the host PC (using USB3/FX3).

The "Synchronous Slave FIFO Interface" has 2 bit addressing mode by default. But I have 2 questions about this:

1) Is there a drawback/advantage in not using any addressing at all? It seems to me it would make the design simpler.

2) Can I change existing the GPIF-II design (sync_slave_fifo_2bit) and remove the addressbus? I see no way to do this, since there are only a few options under "Interface Customizations" in de GPIF-II Designer which don't include any settings for the addressbus, like when starting from scratch. If I start from scratch I see no way of copying the statemachine from the  Slave FIFO Synchronous", so that also seems rather cumbersome.

Any advice is highly appreciated.



1 Solution


After filling a DMA buffer, there is a delay for the socket (associated with the GPIF II thread) to fetch the next DMA descriptor from memory. If you use multiple threads, then after filling one buffer, you can switch address lines and select the next thread.  While the data is filled in the socket associated with this second thread, the socket associated with the first thread can fetch the next DMA descriptor from memory. Hence, this approach will avoid the extra latency incurred by a socket to fetch the next DMA descriptor from memory. Therefore, multiple threads will improve performance.

Best Regards,

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