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USB Superspeed Peripherals

arnova2
New Contributor II

Background: I'm designing an interface where I paired an FPGA with the FX3. I opted to use the "Synchronous Slave FIFO Interface" to interface with the FPGA. The FPGA is paired with 512MB buffer memory. The FPGA should only send streaming (bulk) to the host PC (using USB3/FX3).

The "Synchronous Slave FIFO Interface" has 2 bit addressing mode by default. But I have 2 questions about this:

1) Is there a drawback/advantage in not using any addressing at all? It seems to me it would make the design simpler.

2) Can I change existing the GPIF-II design (sync_slave_fifo_2bit) and remove the addressbus? I see no way to do this, since there are only a few options under "Interface Customizations" in de GPIF-II Designer which don't include any settings for the addressbus, like when starting from scratch. If I start from scratch I see no way of copying the statemachine from the  Slave FIFO Synchronous", so that also seems rather cumbersome.

Any advice is highly appreciated.

 

 

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello,

After filling a DMA buffer, there is a delay for the socket (associated with the GPIF II thread) to fetch the next DMA descriptor from memory. If you use multiple threads, then after filling one buffer, you can switch address lines and select the next thread.  While the data is filled in the socket associated with this second thread, the socket associated with the first thread can fetch the next DMA descriptor from memory. Hence, this approach will avoid the extra latency incurred by a socket to fetch the next DMA descriptor from memory. Therefore, multiple threads will improve performance.

Best Regards,
Jayakrishna

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7 Replies
JayakrishnaT_76
Moderator
Moderator

Hello,

The address lines are necessary to select the active thread into which the data should be written or from which the data needs to be read. Also, the ready and watermark flags status is obtained based on the thread that is addressed. In addition to this, the interface timings mentioned Section 5 - Slave FIFO Access Sequence and Interface Timing of AN65974 needs to be followed to obtain the data correctly. So, we do not recommend to remove the address lines from the slave fifo interface.

Best Regards,
Jayakrishna
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arnova2
New Contributor II

Thanks for your reply

If we would not use addressing, we also need to modify the GPIF statemachine, but we're aware of that.

Unfortunately you didn't answer the question why we need addressing in the first place if it's a single stream we're sending? Would you be so kind to elaborate?

 

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JayakrishnaT_76
Moderator
Moderator

Hello,

I am sorry but I did not understand your question clearly. From your previous responses, I understood that you have to transfer data from FPGA to host only. There is no data transfer from host to FPGA. Did you mean to ask why should the FPGA drive the address lines if there is only single stream? Please let me know if my understanding of your question is correct or not.

Anyhow, on FX3 GPIF II side, we need address lines. As mentioned in my previous response, FX3 when used in Slave fifo operation will sample this address lines to determine the thread through which the data transfer needs to be done. If you do not want to drive these lines from the FPGA, then you can hardwire these lines so that they correspond to the thread used for data transfer.

Best Regards,
Jayakrishna
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arnova2
New Contributor II

Hi,

Correct: I only want to transfer data from FPGA to host. And indeed: I only have a single  (continuous) stream of data to transfer.

But just to be clear: there's no real advantage in using multiple addresses anyway for my scenario (performance wise)?

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JayakrishnaT_76
Moderator
Moderator

Hello,

By "multiple addresses", do you mean to split the data that should be sent to the host into multiple GPIF II threads? If this is the case, then you can improve the performance. But, this would need modifications to be done on FPGA, GPIF II and firmware side. Unfortunately, we do not have a reference project to share for this requirement.

Best Regards,
Jayakrishna
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arnova2
New Contributor II

Hi,

Yes, that's what I meant. My final question is then: Why does it improve performance when multiple addresses/DMA threads are used? Doesn't saturating a single DMA thread use the maximum USB3 speed available?

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JayakrishnaT_76
Moderator
Moderator

Hello,

After filling a DMA buffer, there is a delay for the socket (associated with the GPIF II thread) to fetch the next DMA descriptor from memory. If you use multiple threads, then after filling one buffer, you can switch address lines and select the next thread.  While the data is filled in the socket associated with this second thread, the socket associated with the first thread can fetch the next DMA descriptor from memory. Hence, this approach will avoid the extra latency incurred by a socket to fetch the next DMA descriptor from memory. Therefore, multiple threads will improve performance.

Best Regards,
Jayakrishna

View solution in original post

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