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USB Superspeed Peripherals

New Contributor

I am trying to create a video interface to FX3 GPIF, based on AN75779.  I use FPGA to create simple video signals FV and LV. LV is short with just 8 data (and 8 clks) per LV and 4 LV per FV.  GPIF PCLK  is driven by FPGA.  GPIF counters limit are set to 7 so that it coincides with the 8 data per LV.

To study the state transitions, GPIF outputs '1' to GPIO when in following states highlighted in yellow.  I can only monitor 5 states as GPIF Designer allows maximum only 5 GPIO as output.

pastedImage_0.png

Here is the waveform captured by logic analyzer:

pastedImage_4.png

I notice there is a extra clk with no valid state when transiting from PUSH_DATA_SCK0 to LINE_END_SCK0.  From GPIF designer, there should NOT be a state between  PUSH_DATA_SCK0 and LINE_END_SCK0.

Then I redo the test.  i set GPIF cnt limit to 7, so that incoming data will overflow socket 0 and force GPIF to capture using socket 1.  State transition from PUSH_DATA_SCK0 to PUSH_DATA_SCK1 is correct except there is again 1 unknown state between them.

pastedImage_6.png

Question, will the incoming stream of 8 data (in 8 clks) be correctly captured OR will the extra unknown state  cause the last data to be missed?

Question, why does this unknown state happen?  It does not occur all the time as I can see other state transition without it.

Regards,

Neo

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1 Solution
Anonymous
Not applicable

Hi Neo,

The switching of states in GPIF occurs almost instantaneously.

Now, in Synchronous mode, DR_GPIO signal is driven after 2 clock cycles when early mode is selected and 3 clock cycles when Delayed mode is selected.

In the first logic analyser capture, you can observe that signal D0 is asserted/de-asserted two cycles after LV is asserted/de-asserted.

I suppose, D1 is configured in Delayed mode leading to a 3-cycle latency.

PUSH_DATA_SCK1 will be capturing the correct data and there will be no unknown state as such between state transitions.

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1 Reply
Anonymous
Not applicable

Hi Neo,

The switching of states in GPIF occurs almost instantaneously.

Now, in Synchronous mode, DR_GPIO signal is driven after 2 clock cycles when early mode is selected and 3 clock cycles when Delayed mode is selected.

In the first logic analyser capture, you can observe that signal D0 is asserted/de-asserted two cycles after LV is asserted/de-asserted.

I suppose, D1 is configured in Delayed mode leading to a 3-cycle latency.

PUSH_DATA_SCK1 will be capturing the correct data and there will be no unknown state as such between state transitions.

View solution in original post

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