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In my firmware:CyU3PGpifSocketConfigure (3,CY_U3P_PIB_SOCKET_3,6,CyFalse,1);
When fpga side transfer a short package(32B) to the host,the fisrt 4B data has losed，and the last 4B data was 00-00-00-00.The timing sequence as show in the picture named fpga.png.And the result of host recevied as show in the picture named host.png.The short package that fpga transfered is"0xcc88bb77 0xffff1007 0xffffffff 0xffffffff 0xabcdef01 0xabcdef01 0xabcdef01 0xabcdef01".And the data recevied by the host is" 0xffff1007 0xffffffff 0xffffffff 0xabcdef01 0xabcdef01 0xabcdef01 0xabcdef01 0x00000000".