The DMA block freezes (CX3 MIPI + AR0341)

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
lock attach
Attachments are accessible only for community members.
AvOm_4629506
Level 2
Level 2
First like given Welcome!

Good day!

( Sensor AR0341 4lane 640*480*60fps)

I didn't use your program(from sdk) before. Now I am corrected

I also have a problem with your Linux Studio

1. the CS3 Receiver Configuration tab Is not saved, which means that you need to type everything again every time. see err2.jpg

2. it is not Clear how CS3 MAPI Interface Configuration H_Active is considered as it changes only when PCLK and format are changed. Can you describe it ?

3. my sensor was configured for CPU Clock 192MHz 640*480*60fps 4 lane and an error occurred

Max Output pixel clock cannot transfer CSIData.... see err1.jpg

And I don't understand why: (

Sensor Transmitter CASE Clock 192MHz = 384 Mbps per lane

CS3 PCLK= 87,88MHz RAW10 GPIF16bit. CS3 Recover Data_Rate = 87,88* 10(PixelDepth) = 878,8 Mbps perlane.

4. And still it is unclear opposite Output Pixel Clock the error "Minimum value 301.23" is shown as it so counted ?

At the moment, the project is configured as follows:

I. Sensor AR0341:                                                                                                    CX3:

pastedImage_3.pngpastedImage_4.png

* ignore the name sensor ar0341

  CyU3PMipicsiCfg_t OV4689_RAW10_640_480_60 = 

{

CY_U3P_CSI_DF_RAW10, /* CyU3PMipicsiDataFormat_t dataFormat */

4, /* uint8_t numDataLanes */

1, /* uint8_t pllPrd */

62, /* uint16_t pllFbd */

CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */

CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */

0, /* uint16_t mClkCtl */

CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

640, /* uint16_t hResolution */

0 /* uint16_t fifoDelay */

};

status = CyU3PMipicsiSetPhyTimeDelay(1, 8);

USB works in HS mode. The reset timer is enabled.

Problems:

1 Getting multiple bundles of data CX3 freezes.

Here is a screenshot showing the logs and the location when it was frozen.

When the DMA freezes MIPI continues to work

Here is hsync (yellow) datalane0 (Red) hsync.jpg

Here is Vsync (yellow) datalane0 (Red) vsync.jpg

Here is pclk (yellow) data band 0 (Red) pclk.jpg

0 Likes
1 Solution

Hello,

As i can see from the first image you provided, i still see that the Pixel Clock shows an error in the configuration.
Please confirm that the first configuration is working for you?

But this is all the same only changed blanks and it does not work!

I use USB2.1

CX3_UVC_DATA_BUF_SIZE            (16368)
CX3_UVC_STREAM_BUF_COUNT4

Could you please elaborate the above statement? Did you only change the BUF_SIZE and BUF_COUNT and you are seeing the commit buffer failures and MIPI errors?
Please confirm if you have done anymore changes to the firmware?

Error code = 0x47 corresponds to invalid sequence error.

Please refer to the following KBA: Invalid Sequence Error in Multi-Channel Commit Buffer - KBA218830

This error happens when the host is slow and doesn't issue enough IN tokens to the device as mentioned in the KBA above.

Also, to get an idea of the MIPI errors, please check the following KBA: MIPI-CSI Protocol and Physical Layer Errors in CX3 (CYUSB3065 and CYUSB3064) – KBA228482

Can you please test the same configuration on a different PC and different OS and see if you face the same issues?

Regards,
Yashwant

View solution in original post

8 Replies