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Anonymous
Not applicable

Hi all,

   

We have noticed that FX3 PHY errors count is in strong correlation with activity on GPIF interface. Until data is handled inside FX3, typically errors count stays 0. But if FX3 itself or external FPGA starts to output data to GPIF bus, PHY errors appear.

   

The actual errors rate depends on host chipset type, USB cable length, GPIF interface voltage, etc. Definitely the host plays significant role here - I have a PC with Intel USB chipset on motherboard where the tests can run weeks without any PHY error (if I use short cable and plug the device into right port).

   

But most important - with appearing PHY errors most probably sooner or later the SuperSpeed communication fails.

   

According our experience, also FX3 clock signal quality has significant impact on errors count. You have to keep clock traces on PCB as short as possible (do not even think to clock two chips with same clock!). Otherwise the effect is similar - PHY errors and communication failure.

   

Next is an excerpt from Cypress tech support response:

   

>>>

   

These errors are not part-part dependent, but channel, activity or noise dependent. A noisy set up will produce more of these errors compared to a quiet or less-noisy set up. More activity in the chip may lead to more noise and more of such errors. However, the layers of the communication protocol (USB) are designed to recover from such dynamic errors. IO toggling results in substrate noise. If you see there are 1336 PHY errors with 3.3V IO supply, 42 PHY errors with 1.8V IO supply. Lowering the supply voltage reduces the substrate noise.

   

<<<

   

I definitely agree with tech support. Few PHY errors can be considered natural at SuperSpeed rates. And USB protocol should recover from such errors. But my concern is that in practise USB communication with FX3 fails. Even with perfect host, if you lengthen the cable a bit so that PHY errors start to appear, also the communication starts to fail. I.e. in practise it does not recover from (FX3) PHY errors.

   

dreitz posted in "SuperSpeed interoperability with USB 3.0 controllers" topic:

   

>>>

   

We are using a LeCroy AdvisorT3 to look at the USB 3.0.  We are seeing what they call Interpacket Symbols - IPS, but we never see any bad CRCs or other data.  It only shows Unknown Packets as a problem.  It's like the FX3 starts spewing garbage.

   

When using our device and the data coming from the GPIF interface, it fails.  When we use our device and the USBBulkLoopAuto sample application, we do not see the garbage.

   

<<<

   

Taking all above into account, I start to doubt that FX3 itself fails USB communication due to its internal noise issues. 

   

I attached a test for exploring the issue with Cypress FX3 DVK Device board (CYUSB3KIT-001).

   

Test itself is quite simple - host sends 32-bit toggling (0x00000000/0xFFFFFFFF) data to FX3 and FX3 GPIF automata outputs this data to its pins, causing pins to toggle as well. 

   

FX3 software is built by modifying Cypress Synchronous Slave FIFO (slfifosync) example. The original GPIF state machine is replaced with new one and a Device Vendor Request is implemented for querying FX3 error counters. 

   

Designed GPIF state machine outputs all the host sent data to GPIF pins automatically, without any external control. Plus, it fills automatically IN pipe buffers for sending to host. As there is no external GPIF clock then the automata is modified to use FX3 internal clock. GPIF II project files are located in "FX3device\GPIF II" directory.

   

The most of FX3 source modifications are placed between EXPLORE_GPIF_NOISE defines. Source files are in FX3device subdirectory.

   

Three Windows command line utilities are supplied:

   

1) FX3USBwrite - sends toggling data to FX3 OUT bulk pipe 0x01.

   

2) FX3USBread  - can be used for reading data from FX3 IN bulk pipe 0x81.

   

3) FX3USBerrors - reads FX3 PHY and LINK errors via Control Pipe 0.

   

Utilities source codes are in relevant directories. 

   

Testing scenario:

   

1) On FX3 board, set VIO1..VIO5 to 3.3V (higher bank voltage causes more errors).

   

2) Load FX3GPIFNoise.img to FX3.

   

3) Run FX3USBerrors from command prompt with option "-clear".

   

      FX3USBerrors   -clear

   

This reads FX3 error counters and resets them to 0.

   

4) Read errors with FX3USBerrors several times without "-clear" option. Hopefully error counters stay 0.

   

5) Start sending data to FX3 by launching FX3USBwrite.

   

6) Read errors. Hopefully you will see errors appearing. Few errors per tens of minutes should guarantee USB failure. Leave FX3USBwrite running. After few minutes...days it will exit with error - USB communication has failed.

   

7) Optionally you can launch FX3USBread concurrently as well, this may increase the probability of USB failure.

   

 If there are no errors, try to lengthen the cable or plug FX3 into another USB port. For example, if your PC has USB3.0 ports also at front, try these.

   

 You can also test FX3 with quiet GPIF. For that send constant data 0 to FX3 with command

   

    FX3USBwrite -data=0

   

I expect that error counters remain 0, or at least there are significantly less errors. 

   

Note about Etron chipset/driver. Etron and FX3 just do not cooperate. USB Control Transfers fail randomly at heavy USB throughput and therefore FX3USBerrors may exit immediately with error code 31. Just retry (of course, if FX3USBwrite still runs).

   

Please, test your FX3 and host and give feedback. Especially if you have a set that works reliably with PHY errors. I have 4 different hosts and 2 Cypress FX3 DVK REV3 kits (+ several our own designed prototypes), but no one combination survives FX3 PHY errors.

   

Thanks,

   

kalev

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Anonymous
Not applicable

Hi all,

   

let me update a final solution to your system which may works fine. We have worked out several different designs with FX3 and FPGA now. The FX3 is confirmed to have the problem of noise issues through tests which I guess Cypress did not register the slave fifo control signals since which may increase read latency by one spare cycle. And the FX3 is confirmed to have some problems in the firmware but they are almost fixed in the new SDK release (1.3.3). So the case is that you may update the SDK first.

   

In one of our designs, we noticed severe signal noises on all IO pins. As the VCCO is 1.8V, the witnessed noise reaches 0.6 to 3.0V which causes FX3 slave fifo state machine to die. This design uses a cheap connector with dual line SMT pins. We have solved this problem perfectly by reducing the driving capability to 1/4 the total (3/4 is the default). This design has digital and analog power suppliers splitted and the analog power supplier is able to produce a clean power with ripple less than 5mV Vp-p. The witnessed transmission error is 0 through TBs of data transfer.

   

In another design the USB will fail if the slave FIFO toggles with 0x00000000 and 0xFFFFFFFF. This issue is almost solved by switching to SDK 1.3.3 however sometimes they still become not quite stable. This design uses a single LDO for all 1.2V. This design will witness several bit errors after some GBs of data transfer.

   

In another design, the slave fifo will die but less frequently. This design attaches FPGA and FX3 together on a single 12 layer board which may be able to reduce noises. This design also use splitted power supplier which also witnesses 0 transmission error through TBs of data transfer. Further tests of using 1/4 driving capability showed great slave fifo stability improvement.

   

In another design, the bypass capacitor is not placed at the optimal position. This design is only able to run at 66MHz. If set to 100MHz, it'll die as soon as some seconds. This design uses single supplier for all 1.2V.

   

In conclusion, one want to improve FX3's performance and stability, (1) split power suppliers. For FX3, 4 different power suppliers may be optimal (1.2V VDD, 1.2V VCC, 1.8V VDD, and 1.8V CVDDQ). Today's high frequency DC-DCs (upper than 1.2MHz) can easily reduce output ripple to within 5mV Vp-p. (2) Reduce IO voltage. 1.8V is the best of all. (3) Reduce IO driving capability to 1/4 the value. This helps reduce noises introduced by the IO and transmit line. (4) For some cross board designs, a USB 3.0 redriver may be optimal to maintain signal integrity. The redriver should be placed as close to the receptacle as possible. With some TBs of data transfer the (1) to (3) have been confirmed by us, and (4) is still being verified since we only use the redriver on tiny designs.

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