Hello,
I understand that you are using C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\gpif_examples\cyfxsrammaster (SRAM master) example of the SDK with Superspeed Explorer kit (CYUSB3KIT-003)
For the details about the firmware example, you can refer to the readme.txt file (along with the firmware).
The READ and WRITE to/from SRAM are done using the GPIF state machine which is designed for FX3 to communicate with the SRAM. The state machine generates READ and WRITE signals which enables the SRAM to move data IN and OUT.
A vendor command (SRAM_READ_COMMAND) needs to be sent from the host to read from the SRAM.
The default GPIFstate machine in the firmware drives the address lines (in STATE 0 & STATE 6) based on the value of the address counter (ADDR_COUNT). The counter will increment by 1 with each read/write operation.
If in your application a specific address needs to be driven, the counter value can be modified accordingly.
Note: If you are using CYUSB3KIT-003, only 8 address pins of the CY7C1062DV33 SRAM are connected to FX3 on the CYUSB3KIT-003 kit. This means that only a 1 KB memory region (2 ^ 8 * 32 bits) can be addressed by FX3. So, It is recommended to use address bits as 8 bits.
- Please check if the Jumper J5 is inserted on CYUSB3KIT-003 while using SRAM master firmware.
Please let me know if any queries on this
Regards,
Rashi
GPIF Ⅱ DesignerでInterface Definitionはできたようです。
次のステップはState Machineの設計になると思います。
やりたいことは、指定アドレスからのデータ入出力ですが、考え方など参考資料があればご教示をお願いします。
Hello,
I understand that you are using C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\gpif_examples\cyfxsrammaster (SRAM master) example of the SDK with Superspeed Explorer kit (CYUSB3KIT-003)
For the details about the firmware example, you can refer to the readme.txt file (along with the firmware).
The READ and WRITE to/from SRAM are done using the GPIF state machine which is designed for FX3 to communicate with the SRAM. The state machine generates READ and WRITE signals which enables the SRAM to move data IN and OUT.
A vendor command (SRAM_READ_COMMAND) needs to be sent from the host to read from the SRAM.
The default GPIFstate machine in the firmware drives the address lines (in STATE 0 & STATE 6) based on the value of the address counter (ADDR_COUNT). The counter will increment by 1 with each read/write operation.
If in your application a specific address needs to be driven, the counter value can be modified accordingly.
Note: If you are using CYUSB3KIT-003, only 8 address pins of the CY7C1062DV33 SRAM are connected to FX3 on the CYUSB3KIT-003 kit. This means that only a 1 KB memory region (2 ^ 8 * 32 bits) can be addressed by FX3. So, It is recommended to use address bits as 8 bits.
- Please check if the Jumper J5 is inserted on CYUSB3KIT-003 while using SRAM master firmware.
Please let me know if any queries on this
Regards,
Rashi
Hello,
There are two start states to make the read and write operations independent of each other.
I will explain the write (to SRAM) part of the GPIF state machine.
- The firmware will start the GPIF state machine using this API apiRetStatus = CyU3PGpifSMStart (START, ALPHA_START); where the GPIF state machine will start from the START state.
- The state transition is done based on the transition equations like LOGIC ONE. The transition from one state to another is caused by Boolean expressions formed using the signals on the P-port or events generated as a result of actions. As Logic one means always True the state machine will transition to STATE4.
- STATE 4 will Load/initialize the ADDR COUNTER value. You can refer to section 4.3 of gpif2_designer_guide to know the functionality of the GPIF II actions.
- Then the machine will transition to STATE0 based on the DMA buffer status. DMA_RDY_TH3 will be HIGH (true) when the DMA buffer is fully filled with the data that is to be written to the SRAM. As the DMA buffer size in the firmware is 1024 bytes, the DMA_RDY_TH3 will be asserted when 1024 bytes are filled in the DMA buffer from the USB.
- In STATE0 the address will be driven on the address lines. The value of the address will depend on the current value of the ADDR COUNTER.
- As LOGIC ONE is the transition equation, the STATE0 will immediately transition to STATE 2 where the DATA (DR_DATA) (fetched from the DMA buffer filled by USB block) will be driven on the Data lines and signals WE (DR_GPIO) and CE (DR_GPIO) will be asserted.
- Again the STATE 2 will transition to STATE 3, where the address counter will be incremented (COUNT_ADDR).
- The STATE 3 will transition to STATE 0 when the ADDR counter had not reached the maximum set value (in this case 255). That is why the transition equation is ( !(not) ADDR_COUNT_HIT)
- The STATE 3 will transition to STATE 4 if the ADDRESS COUNTER hits the maximum value set (255).
You can refer to section 3.2 of the gpif_designer_user_guide to understand more about setting the transition equation, input signal settings and output signal settings, state settings.
Regards,
Rashi
