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USB Superspeed Peripherals

New Contributor

Hi Srinath S_16

  I used cyusb314 in slavefifo mode with 16bits bus, and there are two bulk endpoints(0x81 0x01) in it. the dma buffer size corresponding each endpoint is 16*1024 bytes, and the counter of each dma buffer is 2, the pclk is internal(96MHz).  The fpga drive the slavefifo bus in negedge pclk. There ar some srange problems about the slavefifo mode.

       (1) While I transfer data from fpga to cyusb3014(in diection), the slwr should be last 8193 pclk cycles(in word), then the transfered data are right. If the slwr last 8192 pclk cycles, the data still be right(the counter of in dma buffer must be 2), but if i changed the the counter of in dma buffer like 4, the cyusb3014 will be disconnect when i transfer data from fpga to cyusb3014. you can see the sequence diagram in fig1 and fig2(the slwr last 8193 pclk cycles, and the 4 counter of in dma buffer is ok).

       (2) While I transfer data from cyusb3014 to fpga, the transfered datas are correct. if the transfered datas are no more than 256(in word), the data will be transfered only once, the flagc will be 1, and then i can capture the sequence diagram like fig3, but if transfered datas more than 256(like 4096 word), the data must be transfered twice, then the flagc will be 1, and the sequence diagram will be captured like fig4 ,fig5 and fig6, and you can see the counter of captured datas is 8192(in word), why?

       (3) In out direction, while the sloe and slrd are 0 after the counter of 1(fig4), the vaild data will be read at the counter 6(posedge pclk), the pdf of cyusb3014 points that the delay of sloe(slrd) and the bus data is 2 pclk cycles, while i find that the delay in my design is 3( the bus data at the counter 2 3 4 is 0), why?

       (4) I used some gpio pins in the firmware to control fpga, while i find that the enumeration time of cyusb3014 is too long(it looks like 8-9 seconds), if the firmware is programed in 24AA1025. Is that normal? you can see my firmware in appendix.

QQ图片20190603131133.png

fig 1

QQ图片20190603131109.png

fig 2

QQ图片20190603132717.png

fig 3

QQ图片20190603132818.png

fig 4

QQ图片20190603132850.png

fig 5

QQ图片20190603132850.png

fig 6

    Query 1 that i talk about is my fault, fig 1 and fig 2 are the transfer from FPGA to FX3, If the DMA buffer is 16384 bytes, the FPGA should send 8192 words to FX3, not 8193, but if i put the counter of DMA buffer into 4 or more, the usb chip will be disconnected itself, when the  transfer from FPGA to FX3  is done.(#define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U      (4)//in)

    Query 2 is said that If i send no more than 256 words from pc through FX3 to FPGA, the transfer will be correctly, and the 256words will be sent only once from FX3 to FPGA, then FPGA chipscope will capture the flagc active(1, the out dma buffer is not empty); while if i send data more than 256words from fx3 to FPGA, then FPGA chipscope will not capture the flagc active(1, the out dma buffer is not empty) until the data is sent from fx3 to fpga the second time, and the fpga chipscope will capture double data, you can see it in fig 6(ie i send 4096 words from fx3 to FPGA, the fpga will not capture data until the data is sent the second time //CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P (2)). fig 3 and fig4 is the transfer from fx3 to fpga, the counter of data is 16 words, and the data will be set only once. Fig 5 is the partial magnification of fig6, and you can see that the counter of captured data is 8192 words(the counter of data transfered from fx3 to fpga is 4096 words).

、Fig3~fig 6 are the IN transfer.

  Query 4 is said that when the cyub3014 powers on, then the firmware is load from EEPROM to cyusb3014, i will not see the enumerated device in device list until the enumeration is completed, and the duration is 8-9s. Is that normal?

  The GPIF II state machine file is in appendix.

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Moderator
Moderator

Hello,

Query 1:

The FX3 device must ideally not be disconnected when it receives additional data on the GPIF II interface. Instead it throws PIB errors. Can you please check the UART logs that is received before the device gets disconnected?

Query 2:

FLAGC is configured as Thread3_DMA_RDY flag and as active LOW. This means that the FLAGC pin will be LOW whenever the socket pointed to by the thread 3 has got free buffer space and will be HIGH whenever thread 3 does not have space to hold new data. When multiple words of data is being sent, the buffers are continuously filled and there will be no space to hold additional data, hence FLAGC is HIGH. Please let me know why FPGA is not able to receive data in this case.

Query 4:

Usually, loading firmware from EEPROM does not take so much time. What is the frequency of the I2C transfer that is set in the IMG file? is it taking the same duration on different PCs with different OSs?

Best regards,

Srinath S

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1 Reply
Moderator
Moderator

Hello,

Query 1:

The FX3 device must ideally not be disconnected when it receives additional data on the GPIF II interface. Instead it throws PIB errors. Can you please check the UART logs that is received before the device gets disconnected?

Query 2:

FLAGC is configured as Thread3_DMA_RDY flag and as active LOW. This means that the FLAGC pin will be LOW whenever the socket pointed to by the thread 3 has got free buffer space and will be HIGH whenever thread 3 does not have space to hold new data. When multiple words of data is being sent, the buffers are continuously filled and there will be no space to hold additional data, hence FLAGC is HIGH. Please let me know why FPGA is not able to receive data in this case.

Query 4:

Usually, loading firmware from EEPROM does not take so much time. What is the frequency of the I2C transfer that is set in the IMG file? is it taking the same duration on different PCs with different OSs?

Best regards,

Srinath S

View solution in original post

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