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USB Superspeed Peripherals

Anonymous
Not applicable

Hello.
I try to organize Slave FIFO Interface with CYUSB3KIT-003, CYUSB3ACC-006 HSMC Interconnect Board and Altera Cyclone III Starter Board as described in AN65974.
I've compared pinout of CYUSB3ACC-006 with Altera's Starter Board pinout -- and it doesn't match. Some signals from CYUSB3KIT-003, which is needed for Slave FIFO Interface, don't reach FPGA. For example, signal FLAGA. In GPIF II Interface it is CTL[4] (picture 1). CTL[4] on CYUSB3ACC-006 HSMC Interconnect Board attach to pin №100 (picture 2). But on Altera's Starter Board pin №100 connects to 12V and doesn't reach FPGA (picture 3).
So, I don't understand, how Slave FIFO Interface can work? Maybe I miss something. 
Look forward to hearing from you. Thanks.

   

Pic 1 from "CYUSB3014 EZ USB FX3 datasheet", page 32.
Pic 2 from "630-60197-01_CYUSB3ACC-006_HSMC_INTERCONNECT_BOARD_SCHEMATIC", page 3.
Pic 3 from "cycloneiii_sb_3c25", page 11.

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Anonymous
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the pin numbers are slightly misunderstood. If you look at the schematics of CYUSB3ACC-006, you will notice that the pins are divided in three blocks: J1A, J1B, J1C. All the block have 60 pins on the CYUSB3ACC board. But on the FPGA dev kit, you can notice that the part corresponding to J1A connection (J1 block 1) has only 40 pins. So the pin on block 2 of FPGA starts from pin 41 (in CYUSB3ACC it starts with 61). So, there is a mismatch. The pin 100 on CYUSB3ACC is getting connected to pin 80 of FPGA board's J1. Please let me know if you need any further clarification.

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Anonymous
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the pin numbers are slightly misunderstood. If you look at the schematics of CYUSB3ACC-006, you will notice that the pins are divided in three blocks: J1A, J1B, J1C. All the block have 60 pins on the CYUSB3ACC board. But on the FPGA dev kit, you can notice that the part corresponding to J1A connection (J1 block 1) has only 40 pins. So the pin on block 2 of FPGA starts from pin 41 (in CYUSB3ACC it starts with 61). So, there is a mismatch. The pin 100 on CYUSB3ACC is getting connected to pin 80 of FPGA board's J1. Please let me know if you need any further clarification.

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Anonymous
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        That's what I missed! Thank you!   
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