Question about VSYNC_test signal of CX3

HiKu_3811626 · ‎Oct 11, 2020

Hello.

I have a Question about VSYNC_test signal of CX3.

When the MIPI signal is valid data, the VSYNC_test signal is output correctly.

However, when the MIPI signal stops, so does the VSYNC_test signal.

If MIPI signal stops in the middle of the frame, it will be high level.

If MIPI signal stops during V blanking, it will be low level.

Is it possible to set the VSYNC_test signal output to Low level even when the MIPI signal is stopped in the middle of the frame?

JayakrishnaT_76 · ‎Oct 12, 2020

Hello,

The test points on CX3 (VSYNC, HSYNC and PCLK) are driven by the MIPI block of CX3 and are used for debugging purposes only. It is not possible to configure these test points through firmware.

Please let us know why do you want to stop the image sensor in the middle of the frame?

Also, you can call the function CyCx3AppStop() when you stop the image sensor. This function internally does the following:

1. Disable the PLL clocks on the MIPI-CSI interface block and place it in low-power sleep. No data transfers from the Image Sensor to the CX3 will occur while the block is in low power sleep mode.

2. Put the image sensor to sleep.

3. Disable the GPIF Interface.

4. Clean the DMA channel and flush the Endpoint memory.

5. Enable LPM

You can restart the stream by calling the function CyCx3AppStart().

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

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Question about VSYNC_test signal of CX3

Question about VSYNC_test signal of CX3

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