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cnlohr
Level 3
Level 3
10 replies posted 10 sign-ins 5 replies posted

We are using the GPIF bus in master mode and clocking out to an external device, but we need to change the speed at which we are clocking it dynamically, i.e. we need to change the PIB clock parameters after the bus has already been initialized.  What steps do we need to make sure the GPIF bus doesn't fail to operate if we call CyU3PPibDeInit and CyU3PPibInit.

What is the proper procedure to change the clockDiv aspect of the PIB clock?

We also looked into the TRM but were unable to find appropriate registers to modify to alter the clock divisor.

Any advise or direction (to app note, etc.) would be greatly appreciated!

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1 Solution
cnlohr
Level 3
Level 3
10 replies posted 10 sign-ins 5 replies posted

This did not take long to resolve.

 CyU3PGpifDisable(CyFalse); //MUST be CyFalse, and MUST happen BEFORE the PIB Deinit.
CyU3PPibDeInit();
//Reconfigure Clock
CyU3PPibClock_t pibClock;
pibClock.clkDiv = 8; //~400 MHz / 4. or 400 / 8 --- or 384 / 4 or 384 / 8
pibClock.clksrc=CY_U3P_SYS_CLK;
pibClock.isHalfDiv = CyFalse; //Adds 0.5 to divisor
pibClock.isDllEnable = CyTrue; //For async or master-mode
reply[0] = CyU3PPibInit(CyTrue, &pibClock);
reply[1] = CyU3PGpifLoad(&CyFxGpifConfig);

 

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cnlohr
Level 3
Level 3
10 replies posted 10 sign-ins 5 replies posted

This did not take long to resolve.

 CyU3PGpifDisable(CyFalse); //MUST be CyFalse, and MUST happen BEFORE the PIB Deinit.
CyU3PPibDeInit();
//Reconfigure Clock
CyU3PPibClock_t pibClock;
pibClock.clkDiv = 8; //~400 MHz / 4. or 400 / 8 --- or 384 / 4 or 384 / 8
pibClock.clksrc=CY_U3P_SYS_CLK;
pibClock.isHalfDiv = CyFalse; //Adds 0.5 to divisor
pibClock.isDllEnable = CyTrue; //For async or master-mode
reply[0] = CyU3PPibInit(CyTrue, &pibClock);
reply[1] = CyU3PGpifLoad(&CyFxGpifConfig);

 

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