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USB Superspeed Peripherals

Anonymous
Not applicable

Hallo,

   

I have problems with reading data from the GPIF with my FPGA design. The firmware on the FX3 is the synchronous slave fifo example with 2bit address bus. If I try to read the whole buffer in one burst cycle I never get the whole data. There are always five to eight read cycles missing, depending on the received packet size. After some time and in a second read attempt I get the rest of the data. Do you have an idea, how i can get the full packet data in a single burst read?

   

Regards,

   

Bernhard Rohloff

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Anonymous
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Hi Bernhard,

   

Can you please let us know the status of Slave FIFO flag. Are you monitoring the status flag ?

   

Thanks,

   

Krishna.

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