Problems  about the communication between USB  and FPGA

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Anonymous
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Hi:

   

  I have several problems about FX3, when I use the usb3014 transfer data with FPGA. I use the sync slave fifo mode to communicate with the FPGA , problems as following:

   

  First, transfer data from PC to FPGA. When the clk of FPGA lower than 80MHz ,the data will be stopped  to transfer.But when I click the rest of FPGA it will be continue to transfer.

   

 Second, data from FPGA to PC. When the clk of FPGA higher than 70MHz, the access of transfer will be stoped.Then I must to restart the power the device.

   

 The last one,it is also the must important one.Once I find when the transfer stopped ,the endpoints(in/out) of the USB device will be dropped. It looks like the user didn't download the firmware. 

   

 

   

 Does anyone ever meet this issue ?Is there any explanation to that ?

   

 

   

    Thanks for any returns

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2 Replies
Anonymous
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Hi,

   

The reason might be PHY Errors due to noise at high clock. This issiue occurs when your schematic / layout design does not agree with our recommendations. As the errors go beyond a limit there will be USB disconnection automatically.

   

Please confirm if your layout abides by the rules in An70707 Application Note.

   

For more details. please refer:

   

http://www.cypress.com/forum/usb-30-super-speed/superspeed-communication-fails-due-fx3-internal-nois...

   

Regards,

   

-Madhu Sudhan

   

Regards,

   

- Madhu

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Anonymous
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Thanks for the answer. I will learn from the topic. Thank U very much!

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