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USB Superspeed Peripherals

New Contributor II

Hello,

I have created a code for fx3 based on AN5779 in which, i am taking yuy 422 input 16 bit colors per pixel. I have only used additional data enable pin which gives the frame data is available or not. I have designed my own state machine. i ran my firmware and taken input from fpga. but i am not getting any output on vlc? Can you please suggest me what to do and indentify mistakes in it.

Thank you

I am attaching my code..

UART debug messages are not working?  Reference

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Moderator
Moderator

Hello,


Can you please post the UART debug messages along with the board schematics?. In case the schematics are confidential, please let me know.

UART Print:

Application startedÿÿState Machine started

bpfo! 16352

bpfn! 16352

cur state! 4 stat! 0

c

:DMA Reset Event: Frame timer overflow, time period = 200

Application Stopped

Application startedÿÿState Machine started

      bpfo! 0

      bpfn! 0

cur state! 4 stat! 0

c

NOTE: here c means buffer committed

EDIT: Upon looking into your state machine and the UART print, I find that the partial buffer gets committed to the host. This can happen only if the DE! goes LOW and a GPIF call back is raised. Also, in your design, I find that FX3 receives its clock from the external interface. Since, the buffer count was found to be zero from the UART print, I understand that there has been no data transfer happening on the GPIF II interface. So, kindly, probe the CLK and DE pins and share the waveform observed.

Best regards,

Srinath S

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9 Replies
Moderator
Moderator

Hello,

- I don't find any image sensor configurations or pattern data generation in your firmware. Can you please let me know which way are you trying it out?

- Branching at the READDATA state is ambiguous since condition for one of the branches is LOGIC_ONE and the other has got a !DE.

- Also, please let know what DE means and what is it connected to on the external interface.

- Since you have used a 16-bit data bus and a buffer size of 16kB, modify the LD_DATA_COUNT value to 8183. The calculation has been mentioned in the App Note AN75779. Refer to section 3.5.

Best regards,

Srinath S

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New Contributor II

Can you please tell me according to which calculation the buffer count is 8183, As written in AN75779 the calculation should be 8*1024-16 that is 8176 and LD_DATA_COUNT value will be 8175. Am i wrong somewhere?

Thanks

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Moderator
Moderator

Hello,

DMA buffer size would be defined as 16kB - 16bytes (UVC header). So, as per the formula mentioned in the page 18 of the app note, the count can be calculated as follows:

count = [ (producer_buffer_size)/(data_bus_width) ] - 1

producer_buffer_size = 16368

data_bus_width = 2 (in bytes)

Therefore, count = 8183.

In other words, count can be calculated as the number of clock cycles required to fill the DMA buffer. Since the GPIF II interface is 16-bits wide, the number of clock cycles required to fill 16368 bytes of data would be 8184. The count value will be loaded with one less than that, i.e 8183

Best regards,

Srinath S

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New Contributor II

Hello Srinath,

I have done all the changes suggested by you, but still not working.

I have seen debugging messages through which i can surely say that the buffers coming from gpif state machines are empty.

After one buffer the fx3 stops working and i am not getting any debugging messages too. whats wrong in it?

Thanks

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Moderator
Moderator

Hello,


Can you please post the UART debug messages along with the board schematics?. In case the schematics are confidential, please let me know.

UART Print:

Application startedÿÿState Machine started

bpfo! 16352

bpfn! 16352

cur state! 4 stat! 0

c

:DMA Reset Event: Frame timer overflow, time period = 200

Application Stopped

Application startedÿÿState Machine started

      bpfo! 0

      bpfn! 0

cur state! 4 stat! 0

c

NOTE: here c means buffer committed

EDIT: Upon looking into your state machine and the UART print, I find that the partial buffer gets committed to the host. This can happen only if the DE! goes LOW and a GPIF call back is raised. Also, in your design, I find that FX3 receives its clock from the external interface. Since, the buffer count was found to be zero from the UART print, I understand that there has been no data transfer happening on the GPIF II interface. So, kindly, probe the CLK and DE pins and share the waveform observed.

Best regards,

Srinath S

View solution in original post

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New Contributor II

Hello Srinath, srnt

I have not done any image sensor configuration because, fpga is sending the data directly and no configuration is needed. fpga is giving out 84MHz clock. one data enable signal which is used to know frame start and frame end, and there is 16 bit data.

I am branching READDATA state for one branch condition is logic one because LD_DATA_COUNT condition cannot be used with COUNT_DATA so when data is enable then it will go to READDATA for loading the data count, and after loading the dat count it will move to count which will count the data in the buffer. if the buffer is not hit then it will again go to IN_DATA for taking input from FPGA and when any of signal either DE or DATA_COUNT_HIT enters. It forwards the buffer to interrupt sequence. Thats my logic.

DE is connected to data enable pin from fpga source which tell start and end of frame

Regards

Sagar

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Moderator
Moderator

Hello Sagar,

- Please let me know if the UVC headers are added in the FPGA or in the FX3.

- Since you have used LOGIC_ONE as the condition for branching at READDATA state, the state machine does not switch to PARTIAL_BUF state and will be caught in loop between READDATA and COUNT states.

- You can modify the implementation such that LD_DATA_COUNT action is performed in a dummy state before READDATA state and the IN_DATA and COUNT_DATA actions can be performed in READDATA state.

- Also, as I had mentioned in the previous interaction, modify the LD_DATA_COUNT value.

Best regards,
Srinath S

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New Contributor II

Headers are added in FX3 itself and i have modified the state machine by adding the dummy state in between, i have also modified the LD_DATA_COUNT and buffer size to 8183, I am adding header in FX3S itself.

Please look at my state machine State_Machine.PNG

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Moderator
Moderator

Hello Sagar,

You can remove the COUNT state and add the COUNT_DATA action in the READDATA state itself. The branching condition from READDATA to FULL_BUFFER can be set as DATA_CNT_HIT.

Please let me know the results with the modified state machine. Also, please capture the UART logs and USB traces if possible in case of failure.

Best regards,

Srinath S

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