Powering the FX3 / Using a hub on D+ and D-

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WaRa_4824346
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I need to achieve low standby power consumption in a system with an FX3 and a Xilinx FPGA.  This system primarily remains in a low power idle state for 99% of the time where neither the FX3 or FPGA is being used. 

Referring to the block diagram below, the PSoC is powered continuously through the LDO.  The PSoC controls switching regulators that power a USB host, the FX3 and the Xilinx.  The PSoC also performs aggressive power management to maximize battery life.

WaRa_4824346_0-1611302655092.png

The PSoC turns on power to the FX3 and the Xilinx FPGA.  All of the FX3's core VDD(x) and IO VIO(x) supplies are powered.  The FPGA's IO banks connected to the FX3 are powered as well to avoid the FX3 driving an unpowered FPGA or vice versa.

Later, the PSoC will apply power to the USB Host system which in turn powers VBUS on the USB connector.  VBUS is used to hold the FX3 in RESET (using an RC network) until VBUS is stable.

Questions:

1. Will this method of powering the FX3 work? 

2.  I'm confused about the use of VBATT versus VBUS FX3 signals.    The Super Speed Explorer connects VBUS on the USB connector to the FX3's VBUS signal.  The FX3's VBAT signal is not connected on the SSE.   The FX3 DVK connects a select-able power supply(+5V,+3.3,+2.5) voltage or a battery through a diode OR to the FX3's VBAT signal.  VBUS from the USB connector is connected to the FX3's VBUS signal.    Other FX3 based boards connect the VBUS line from the USB connector to both VBAT and VBUS on the FX3.  I'm not sure what is the correct usage for my application.  Please explain.

3. I have other H/S USB devices that would share one USB Gen 3 connector.  It is possible to insert a CY7C65642 USB hub on the D+ and D- signals?

Thanks for your help!

Wayne

3.

 

 

 

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1 Solution

Hello Wayne,

2. If I understood your reply correctly, you recommend that  VBAT is connected to the switched power source and VBUS be connected to USB connector to monitor USB host activity.  Aye, sir!

>> Yes, your understanding is correct.

 There are several H/S USB devices that want to share that Gen 3 connector (if possible)

>> The hub can be used. If the hx2vl is in self powered mode, it should be reset once host is connected. You can tie hx2vl reset to usb vbus. Also, please let us know if fx3 will be used only as usb 3.0 device. If yes, you can disable the usb 2.0 as mentioned in this KBA Enabling FX3 Only for USB 3.0 Applications – KBA21... - Cypress Developer Community

1. I'm not aware of all of the firmware implications of connecting the FX3's RESET signal to VBUS on the USB connector.  Perhaps, the FX3 should allowed to boot once its power rails are stable.  Do you recommend holding the FX3 in RESET until VBUS on the USB connector is stable or just until the FX3 power rails are stable?  Many USB hubs prefer to be in RESET until VBUS is applied.

>> Please refer to this KBA Power Up Sequence for FX3 – KBA221826 - Cypress Developer Community and the reset sequence in FX3 datasheet.

2.  The synchronous slave FIFO bus is bidirectional.  Ensuring signal integrity for bidirectional LVCMOS buses is always a challenge.   I use HyperLynx and Infineon provides IBIS models so I can always run a signal integrity simulation to check.  Do you have any specific recommendations for signal integrity concerning the FX3's synchronous slave FIFO bus?

>> As per AN70707, if the GPIF lines are to be routed for more than 5 inches or routed through a medium that can cause impedance mismatch, we recommend doing signal integrity simulation using the EZ-USB FX3 IBIS model, and come up with a termination.

Regards,
Rashi

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Rashi_Vatsa
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Hello Wayne,

1. Will this method of powering the FX3 work? 

>> Please confirm if this architecture is different from the one shared in the old thread FX3 "Self Powered" Architecture Questions - Cypress Developer Community 

2.  I'm confused about the use of VBATT versus VBUS FX3 signals.    The Super Speed Explorer connects VBUS on the USB connector to the FX3's VBUS signal.  The FX3's VBAT signal is not connected on the SSE.   The FX3 DVK connects a select-able power supply(+5V,+3.3,+2.5) voltage or a battery through a diode OR to the FX3's VBAT signal.  VBUS from the USB connector is connected to the FX3's VBUS signal.    Other FX3 based boards connect the VBUS line from the USB connector to both VBAT and VBUS on the FX3.  I'm not sure what is the correct usage for my application.  Please explain.

>> Super Speed Explorer kit is bus powered. All the LDOs which power FX3  are powered using VBUS and VBATT is left unconnected.

FX3 DVK has provision to either be in self powered mode (FX3 is powered by on board power source (battery) or bus powered mode (FX3 powered by VBUS)

VBATT is used to power only USB I/O when the device is in self powered mode.  VBATT/VBUS can be turned OFF if USB is not used. If the USB port is used, one or both supplies must be present.

As per the block diagram, Fx3 is powered using on board power source so you can go for self powered mode. VBATT can be connected to respective power source to power the USB I/O and VBUS can be connected to the host so that FX3 can detect when  USB host is connected.

3. I have other H/S USB devices that would share one USB Gen 3 connector.

>>Please elaborate on this

Regards,
Rashi
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Rashi

Thanks again for your amazingly prompt reply.  Comments about your replies are below...

Comments:

1.  Yes, the diagram attached in this email thread is a new block diagram that reflects your previous about comments powering all VIO continuously.  Also, we will not use the FX3 for USB connectivity AND power management.  A  PSoC5LP was added that manages power to the system which avoids many problems with having the FX3 be powered while the FPGA is not.

2. If I understood your reply correctly, you recommend that  VBAT is connected to the switched power source and VBUS be connected to USB connector to monitor USB host activity.  Aye, sir!

3. Due the idiosyncrasies of the mechanical design, I would like to use only one USB Gen 3 Type B connector.  The FX3 is the ONLY device needs that to run at Gen 3 speeds (what a relief).    There are several H/S USB devices that want to share that Gen 3 connector (if possible), they are:

1. The FX3 itself for H/S only hosts

2. A ULPI transceiver that is connected to the Xilinx FPGA (H/S only)

3. A USB to UART and JTAG bridge (H/S only)

4. The previously PSoC5LP.  This allows the USB host to send system power management commands like "turn off for 4 hours or until a wake up signal is asserted" to the PSoC5LP.  (F/S only)

I have seen at least one board using the FX3 and a USB hub on the H/S speed interface.  Someone has made this work.

New Questions:

1. I'm not aware of all of the firmware implications of connecting the FX3's RESET signal to VBUS on the USB connector.  Perhaps, the FX3 should allowed to boot once its power rails are stable.  Do you recommend holding the FX3 in RESET until VBUS on the USB connector is stable or just until the FX3 power rails are stable?  Many USB hubs prefer to be in RESET until VBUS is applied.

2.  The synchronous slave FIFO bus is bidirectional.  Ensuring signal integrity for bidirectional LVCMOS buses is always a challenge.   I use HyperLynx and Infineon provides IBIS models so I can always run a signal integrity simulation to check.  Do you have any specific recommendations for signal integrity concerning the FX3's synchronous slave FIFO bus?

As always, your guidance is VERY much appreciated!

Wayne

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Hello Wayne,

2. If I understood your reply correctly, you recommend that  VBAT is connected to the switched power source and VBUS be connected to USB connector to monitor USB host activity.  Aye, sir!

>> Yes, your understanding is correct.

 There are several H/S USB devices that want to share that Gen 3 connector (if possible)

>> The hub can be used. If the hx2vl is in self powered mode, it should be reset once host is connected. You can tie hx2vl reset to usb vbus. Also, please let us know if fx3 will be used only as usb 3.0 device. If yes, you can disable the usb 2.0 as mentioned in this KBA Enabling FX3 Only for USB 3.0 Applications – KBA21... - Cypress Developer Community

1. I'm not aware of all of the firmware implications of connecting the FX3's RESET signal to VBUS on the USB connector.  Perhaps, the FX3 should allowed to boot once its power rails are stable.  Do you recommend holding the FX3 in RESET until VBUS on the USB connector is stable or just until the FX3 power rails are stable?  Many USB hubs prefer to be in RESET until VBUS is applied.

>> Please refer to this KBA Power Up Sequence for FX3 – KBA221826 - Cypress Developer Community and the reset sequence in FX3 datasheet.

2.  The synchronous slave FIFO bus is bidirectional.  Ensuring signal integrity for bidirectional LVCMOS buses is always a challenge.   I use HyperLynx and Infineon provides IBIS models so I can always run a signal integrity simulation to check.  Do you have any specific recommendations for signal integrity concerning the FX3's synchronous slave FIFO bus?

>> As per AN70707, if the GPIF lines are to be routed for more than 5 inches or routed through a medium that can cause impedance mismatch, we recommend doing signal integrity simulation using the EZ-USB FX3 IBIS model, and come up with a termination.

Regards,
Rashi
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