cancel
Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals

HuEl_264296
New Contributor II

Hi,

I used my oscilloscope to sample the MIPI data line on an OV7251 camera. The camera has a resolution of 640x480, 8 bits per pixel, and is transmitting at 60fps. It looks like it's using a MIPI clock of 400MHz, and has 1 data lane.

How should I configure CX3 MIPI Receiver?

1. Does the H-Blanking period refer to the 23.15us "no data" period between the individual lines? In my example they are nearly three times longer than the active period!

2. Does the V-blanking period refer to the 1.32ms period between the 15.34ms active frame time?

3. Do I set the H-Blanking period to 23.15/8.52 * 640 ?

4. Do I set the V-Blanking period to 1.32/15.34 * 480 ?

5. Presumably I set the CSI clock to 400MHz?

6. Do I set the Pixel clock to more than (640+1740) x (480+42) x 60  ( =  74.54MHz)

Many thanks

Hugo

Frame_Period.png

Individual_Lines.png

Single_Line.png

0 Likes
1 Solution
KandlaguntaR_36
Moderator
Moderator

Edited:

Hello,

The MIPI Multipacket example is shown below: (Source: http://caxapa.ru/thumbs/799244/MIPI_Alliance_Specification_for_Camera_S.pdf ). Here you can see that the VVALID is active from FS to FE. The timing of VVALID includes SoT, PH,FS,LS, PF,FE,LE,EoT. Similarly HVALID or DVALID.

pastedImage_1.png

Since you confirmed that the MIPI CSI is operating at 400 Mhz. Hactive time would be = 640*8 / clock / 2 (DDR clock) = 6.4 us.

By including the PH and PF, this time became 8.52 us in your case. You can consider the 23.15 us as Hblanking.

Answering your queries:

1. Does the H-Blanking period refer to the 23.15us "no data" period between the individual lines? In my example they are nearly three times longer than the active period!

2. Does the V-blanking period refer to the 1.32ms period between the 15.34ms active frame time?

3. Do I set the H-Blanking period to 23.15/8.52 * 640 ?

4. Do I set the V-Blanking period to 1.32/15.34 * 480 ?

5. Presumably I set the CSI clock to 400MHz?

6. Do I set the Pixel clock to more than (640+1740) x (480+42) x 60  ( =  74.54MHz)

Answer:

Your calculations are correct for above 6 questions.

Can you please confirm whether you are able to see the video properly?

Also Probe HSync, VSync and PCLK_test signals of CX3 chip to findout the actual Hactive, Hblanking, Vactive and Vblanking.

Sridhar

View solution in original post

0 Likes
1 Reply
KandlaguntaR_36
Moderator
Moderator

Edited:

Hello,

The MIPI Multipacket example is shown below: (Source: http://caxapa.ru/thumbs/799244/MIPI_Alliance_Specification_for_Camera_S.pdf ). Here you can see that the VVALID is active from FS to FE. The timing of VVALID includes SoT, PH,FS,LS, PF,FE,LE,EoT. Similarly HVALID or DVALID.

pastedImage_1.png

Since you confirmed that the MIPI CSI is operating at 400 Mhz. Hactive time would be = 640*8 / clock / 2 (DDR clock) = 6.4 us.

By including the PH and PF, this time became 8.52 us in your case. You can consider the 23.15 us as Hblanking.

Answering your queries:

1. Does the H-Blanking period refer to the 23.15us "no data" period between the individual lines? In my example they are nearly three times longer than the active period!

2. Does the V-blanking period refer to the 1.32ms period between the 15.34ms active frame time?

3. Do I set the H-Blanking period to 23.15/8.52 * 640 ?

4. Do I set the V-Blanking period to 1.32/15.34 * 480 ?

5. Presumably I set the CSI clock to 400MHz?

6. Do I set the Pixel clock to more than (640+1740) x (480+42) x 60  ( =  74.54MHz)

Answer:

Your calculations are correct for above 6 questions.

Can you please confirm whether you are able to see the video properly?

Also Probe HSync, VSync and PCLK_test signals of CX3 chip to findout the actual Hactive, Hblanking, Vactive and Vblanking.

Sridhar

View solution in original post

0 Likes