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USB Superspeed Peripherals

CoCo_4528381
New Contributor

Hello,


I have some configuration problems when using the cx3 with a custom camera board.

More specifically, I have Mipi problems when configuring the CX3 with 4 Tx lanes receiving RAW8 data. Before going into details, I just want to anticipate the following:

-between camera and cx3 I have an FPGA stage where I convert the parallel pixel into serial (CSI-2), hence I can reconfigure the data format.
-The cx3 successfully worked with 2 Tx lanes for both RAW10 and RAW8 format (I set the GPIF bus width to 16 in both cases as explained in several threads, otherwise e-camview wouldn't work with a GPIF bus width set to 8).
-The cx3 successfully worked with RAW10 format configured with 4 TX lanes (meaning that I don't have routing problems with 4 TX lanes).

The parameters I am using are the the following:

- CSI clock 80 MHz

- 4 data lanes

- non-continuous clock mode

- Pixel clock 80.0 MHz

- Video format: RAW8

- Resolution: 1024x200

- H-blanking: 2152

- V-Blanking: 73

- FPS: 88

- THS prepare 100 ns, THS-zero 150 ns.

This is how I configured the CX3:

CyU3PMipicsiCfg_t Camera_control =

{

    CY_U3P_CSI_DF_YUV422_8_0,  /* CyU3PMipicsiDataFormat_t dataFormat */

    4,                          /* uint8_t numDataLanes */

    1,                /* uint8_t pllPrd */

    79,            /* uint16_t pllFbd */

    CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */

    CY_U3P_CSI_PLL_CLK_DIV_4,    /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

    CY_U3P_CSI_PLL_CLK_DIV_4,    /* CyU3PMipicsiPllClkDiv_t parClkDiv */

    0,                        /* uint16_t mClkCtl */

    CY_U3P_CSI_PLL_CLK_DIV_2,    /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

    1024,                /* uint16_t hResolution */

    300                            /* uint16_t fifoDelay */

};


I also add the following picture from the config file to confirm that I do not have errors:

cypress_report2.PNG

I configured it in order to append 8 bits of zero to each RAW8 pixel (through CY_U3P_CSI_DF_YUV422_8_0) and to have a number of bytes per frame equal to 1024x200*2bytes= 409600 bytes. This operation properly worked when the system was configured with 2 Tx lanes.
I also used the phy time delay API properly.
When I run e-cam view the error I get on the UART port is the following:

cypress_report1.PNG

As you can see I constantly have crc errors and I think this is related to how I configured the MIPI interface. I'm not able to constantly receive a full frame. Do you have suggestions on where the problem could be?

Thanks in advance.

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3 Replies
JayakrishnaT_76
Moderator
Moderator

Hello,

Please refer to the following KBA that contains information regarding MIPI CSI Protocol and Physical Layer Errors in CX3.

MIPI-CSI Protocol and Physical Layer Errors in CX3 (CYUSB3065 and CYUSB3064) – KBA228482

From the KBA mentioned above, crc error count will be incremented when an HS packet is received with CRC errors. Please let us know if you are getting any MIPI errors when you were trying to stream the video in RAW10 format using four lanes. If you were not getting errors, then please verify the MIPI stream for RAW8 format using four lanes.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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CoCo_4528381
New Contributor

Hello Jayakrishna,

I confirm that I am not getting MIPI errors when working with RAW10 using four transmission lanes. Could you please specify what do you mean by verifying the MIPI stream for RAW8?

Best Regards,

Costantino

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Hemanth
Moderator
Moderator

Hi Constantino,

Can you post entire Cx3 receiver configuration page?

In non-working case, data lanes is 4. Input data format on the MIPI lanes is RAW8, Output data format is YVYU, GPIF Bus width is 16. Am I right?

But the following is working:

data lanes is 4. Input data format on the MIPI lanes is RAW10, Output data format is YVYU, GPIF Bus width is 16.

In the above log, why is the Frame Sz changing?

Regards,

Hemanth

Hemanth
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