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USB Superspeed Peripherals

New Contributor

I want to use the Cypress USB 3.0 Dev Kit to push out a 5gb signal and measure that signal on various analyzers.  I stumbled onto the sourcing project and I'm starting to learn how it works.  Since I'm in a time crunch I'm hoping I can get some feedback on if what I want to do is even possible and any tips on how to get it done.

How can I force the dev kit to just send out a bit sequence repeatedly with no endpoint (not connected to PC)? The end of the cable will go into a breakout board (which will provide power) such that I can tap into the data bus signals and measure them on my scope.

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Moderator
Moderator

Hi,

Without a Host, it is not possible to send out a bit sequence out of the USB device. Please let me know your end goal so that we can help accordingly. Also can you please mention which sourcing project you are referring to?

Regards,

Hemanth

Hemanth

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Moderator
Moderator

Hi,

Without a Host, it is not possible to send out a bit sequence out of the USB device. Please let me know your end goal so that we can help accordingly. Also can you please mention which sourcing project you are referring to?

Regards,

Hemanth

Hemanth

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New Contributor

The example project I started with is located at:

Cypress\EZ-USB FX3 SDK\1.3\firmware\basic_examples\cyfxisosrc

From the project file cyfxisosrc.c description:

A constant patern data is loaded onto the OUT channel DMA buffer whenever the buffer is available.

   CPU issues commit of the DMA data transfer to the consumer endpoint which then gets transferred

   to the host. This leads to a constant source mechanism.

This is pretty close to what I want to do. I was hoping there would be a way to make the firmware just push out this bit pattern without an endpoint somehow. The end goal being that I need a high speed differential data source as a piece of a product I am designing. Since USB transceivers are cheap and ubiquitous this would be a perfect source for my differential signal in the 5gig range. I was trying to avoid digging into FPGA designs as it is not something I have done before so it will take more time for me to get up to speed.

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