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USB Superspeed Peripherals

amjoc_3854616
New Contributor II

Hi,

I'm trying to read/write data (size : 8MB) to FPGA through GPIF2 interface with fx3 as a master. Example code used for this purpose is AN87216.

I've changed according to my needs. Read will start by checking FLAGA status, instead of that i used FW_TRG with INTR_CPU at RD_CTRL state. When i try to read data from Control center utility, only (2048*16) bytes of data is read. If i try to read again, the following error is shown.

BULK IN transfer

BULK IN transfer failed with Error Code:997

Can you help with start reading data without checking the flag status? I need to get complete data without data loss?

Attaching firmware code and .cydsn folder.

Message was edited by: amal john

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1 Solution
abhinavg_21
Moderator
Moderator

Hi Amal,

You are using !DMA_RDY_TH0 from "DO_IN_DATA" to "RD_WR_IDLE" when DMA buffer gets exhausted. Please note that there is a delay in the propagation of this flag status. And hence you are losing 4 bytes when buffer gets full. Please use DMA_WM_TH0 (watermark flag) here. After watermark flag is received kindly do INDATA according to watermark value set  and then reach "RD_WR_IDLE" state. Use "DMA_RDY_TH0" in all other transaction equations.

Thanks & Regards
Abhinav

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7 Replies
SrinathS_16
Moderator
Moderator

Hello,

Can you please re-attach the GPIF II designer project? I find that you have only attached the .cyfx file. It is essential that you provide the entire .cydsn folder.

Best regards,

Srinath S

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amjoc_3854616
New Contributor II

Hi,

Thanks for your reply.

Have attched the .cydsn folder, please check.

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amjoc_3854616
New Contributor II

Hi,

Did you guys get the error in my code?

And is there any way to get the FPGA side deign for XIlinx for the gpif2 interface with fx3 as a master and fpga as a slave?

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SrinathS_16
Moderator
Moderator

Hello,

The AN87216 uses a 32-bit GPIF II interface with a buffer size of 2048 bytes. So, the ADDR_COUNT limit value was set to 511 (4-bytes of data * 512 = 2048 bytes (one buffer size)). In your case, you have used a 16-bit GPIF II interface with the same state machine. Please modify the ADDR_COUNT limit value to 1023 in your state machine and test it.

We do not have an example firmware that implements FPGA slave.

Best regards,

Srinath S

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amjoc_3854616
New Contributor II

Hi,

I did the changes, still at the end of buffer count hit 4bytes of data ar e missed.

That is my buffer size is 2048 * 16, at the end of every 2048 bytes 4 bytes of data are missed.

I've shared the code and the gpif designer. I have also attached the screenshot of the data miss seen in Control Center utility.

How can this be rectified?

I tried using DMA_WM_TH0 instead of DMA_RDY_TH0 in gpif designer, data was not even received at P-port. Is there any changes required in firmware for using DMA_WM_TH0?

Please do help, i"ve been stuck with this for weeks.

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amjoc_3854616
New Contributor II

Hi, can you please look into the issue? It's urgently needed to be rectified.

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abhinavg_21
Moderator
Moderator

Hi Amal,

You are using !DMA_RDY_TH0 from "DO_IN_DATA" to "RD_WR_IDLE" when DMA buffer gets exhausted. Please note that there is a delay in the propagation of this flag status. And hence you are losing 4 bytes when buffer gets full. Please use DMA_WM_TH0 (watermark flag) here. After watermark flag is received kindly do INDATA according to watermark value set  and then reach "RD_WR_IDLE" state. Use "DMA_RDY_TH0" in all other transaction equations.

Thanks & Regards
Abhinav

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