I have this state machine segment, I use LV to trigger the DMA to DR_DATA onto the parallel data bus. I capture the data using the timing
relationship similar to "cs_n = 0 & we_n = 0"--> "data" of SRAM.
In the logic analyzer I could see an extra 32-bit of unknown data. What's the latency for me to capture the data?
When I set the data count to 16384 with incr = 4, after pulse the LV for 4096 pulses, the state machine stays at DL_WAIT instead of moving onto DOWNLOAD_DONE via DATA_CNT_HIT. Anything wrong with my state machine?
