I have this state machine segment, I use LV to trigger the DMA to DR_DATA onto the parallel data bus. I capture the data using the timing
relationship similar to "cs_n = 0 & we_n = 0"--> "data" of SRAM.
In the logic analyzer I could see an extra 32-bit of unknown data. What's the latency for me to capture the data?
When I set the data count to 16384 with incr = 4, after pulse the LV for 4096 pulses, the state machine stays at DL_WAIT instead of moving onto DOWNLOAD_DONE via DATA_CNT_HIT. Anything wrong with my state machine?
Does the state machine go to DOWNLOAD_DONE after 4097 pulse?
You should check if you are initializing the counter with 0, and try with counter value 16380. Also, do not set the reload the counter fo limit hit option.
Thank you Nishant.
I will test that in my next RTL run.
My problem is, after I capture the LV and fx3_data in integrated logic analyzer in Xilinx, I can see the word after the 1st LV pulse is not the data the memory I initialized/committed in USB Suite. The 2nd value after LV is the data, and all values above are correct, and the tail of the data in my FPGA SRAM is short of the 4 bytes too.
I could just ignore 1st value and use 4097 cycles but in a regulated industry I don't like such hacks.