Image was broken (CX3)

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TaKI_297676
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10 questions asked 25 sign-ins 10 replies posted

I am testing CX3.

In high speed image, image was broken.

TaKI_297676_0-1611625408985.png

Right side of image is broken. 

(UVC , all registers and buffer size is same to default value. Source is made by "EZ USB Suit".

 

Please let me know how to fix this problem.

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Rashi_Vatsa
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Hello,

The CX3 MIPI Receiver configuration seems fine now.

It seems you are using CX3 Denebola kit for testing, please share the UART debug prints when the streaming is started. Please enable PRINT_FRAME_INFO macro in the firmware and take the UART debug prints

- You can also set the Phy Time Delay value as per the CX3 MIPI receiver configuration manually

CyU3PMipicsiSetPhyTimeDelay API can be used to set phy time delay. This function should be not be called while the MIPI-CSI PLL clocks are active. Either call after calling CyU3PMipicsiSetIntfParams() with wakeOnConfigure set to False (before  calling CyU3PMipicsiWakeup() ), or call CyU3PMipicsiSleep() before calling this API.

The value to set in your case is 0x12 (18 decimal).

Also confirm if the CX3 system clock is configured as 403.2 MHz by clock setting like this

clockConfig.setSysClk400 = CyTrue;

Regards,
Rashi

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Rashi_Vatsa
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Hello,

From the description, I understand that the video streaming is not as expected when streamed through USB 2.0 Is that correct?

If yes, please let me know the video resolution (frame size) (H active * V active* bits/pixel) and fps. Also, share the UART debug prints while streaming is done.

Regards,
Rashi
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It is working on USB3.0.

 

Video Resolution is 640x1200 (RGB24)., 115fps.

MIPI setup is belows

TaKI_297676_0-1611718142998.png

When MIPI clock was 300MHz(same resolution with 100fps), same problem was happened.

UART debug didn't print any thing. (I think it means that sensor or cx3 is working well).

 

Regards 

Ted Kim

 

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Hello Ted,

The maximum CSI clock is limited to 300 MHz for 4 data lanes as the maximum GPIF bus bandwidth (2.4Gbps) is the bottleneck.

The data will be lost as the input data rate exceeds the maximum supported GPIF bus bandwidth. 

I have come across this thread Image Problem on CX3 - Cypress Developer Community for which the vertical blanking period need to be increased to >400us. As 300 MHz is the maximum CSI clock frequency that can be used I have reduced the H blanking period to get the required V blanking period. Please try using this configuration (attached) and let me know the results.

Regards,
Rashi
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I asked already this problem.

Your member, Hemanth mentioned belows

=================================

With the current configuration vertical blanking is only 200us. It should be greater or around 400us.

Can you make following changes and test:

CSI clock: 400MHz(Make sure that transmitter is also configured for this value);

Hblanking: 160pixel; VBlanking: 50line

With this vertical blanking will be increased to 400us.

======================================================

And I asked one more time about max speed.

 

When I set 300MHz, Same problem was happened. 

I can't change horizontal blank shorter because of sensor.

(possible longer)

 

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Hello,

V blanking period > 400us is a requirement for Cx3. So to increase the v blanking period, v active needs to be reduced as  v total is constant (to maintain the FPS). V active period can be reduced by either reducing H active or H blanking period.

As mentioned by you that the sensor cannot support lower h blanking, try reducing the fps  such that the v blanking period > 400us

Regards,
Rashi
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Hello,

 

I tested one more time as your suggestion.

4ch MIPI 300MHz, and Vertical Blank is about 470us.

TaKI_297676_0-1611812165245.png

But, i can't fix that problem.

We are testing CX3 as RDK.

TaKI_297676_1-1611812269932.png

 

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Rashi_Vatsa
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5 likes given 500 solutions authored 1000 replies posted

Hello,

The CX3 MIPI Receiver configuration seems fine now.

It seems you are using CX3 Denebola kit for testing, please share the UART debug prints when the streaming is started. Please enable PRINT_FRAME_INFO macro in the firmware and take the UART debug prints

- You can also set the Phy Time Delay value as per the CX3 MIPI receiver configuration manually

CyU3PMipicsiSetPhyTimeDelay API can be used to set phy time delay. This function should be not be called while the MIPI-CSI PLL clocks are active. Either call after calling CyU3PMipicsiSetIntfParams() with wakeOnConfigure set to False (before  calling CyU3PMipicsiWakeup() ), or call CyU3PMipicsiSleep() before calling this API.

The value to set in your case is 0x12 (18 decimal).

Also confirm if the CX3 system clock is configured as 403.2 MHz by clock setting like this

clockConfig.setSysClk400 = CyTrue;

Regards,
Rashi
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