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USB Superspeed Peripherals

Anonymous
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I try my best,but it did not work,any one who can help me to configure the slavefifo

   

recieve data from fpga?help me.please...

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Anonymous
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IM also trying to do the same thing. For slave fifo to work wen need to configure GPIF II interface. There is one pdf AN65974. just go through that. it is tellling about gpif interface. but on fpga side we should do some controller stuffs that is able to monitor flags and also provide the control signals. Which board are you using.  i mean SDK ?

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Anonymous
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I using the SDK1.0 the latest SDK.

   

Did you use the fifo?

   

My fpga is always sending data to FX3.

   

I did not use the flag,I just want to know the fifo is working or not,but there is no data receive from the fifo.

   

so,please help me...

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New Contributor II

Hi,

   

The important control signals for FPGA to FX3 for slave fifo are:

   

FIFO ADDR   : both low
SLCS  = low
PKTEND = high
SLOE = high
PCLK should run at 100 MHz but run at 50MHz as in the past this didn't work properly  at 100MHz and maybe still is an issue
SLWR is active low and this will write data to into the FX3 buffers

   

FLAGS A and B - but can be ignored if flow control not required for test purposes

   

If these signals are present between the FPGA and the FX3 then the example synchronous slave fifo firmware provided by Cypress should work.

   

Are you able to get some of the other firmware examples working okay?

   

Sodafarl

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Anonymous
Not applicable

thank you very much.

   

the clk must be 100MHZ?

   

the pktend must be set high?

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New Contributor II

Hi,

   

PKTEND is normally high - only use when you want to transfer a  a short packet across USB.

   

Maximum frequency of PCLk is 100MHz but can run a lot slower. If slave fifo does not work at 100MHz try slower say 50Mhz.

   

See this link http://www.cypress.com/?app=forum&id=167&rID=54889 for some details about past issue with PCLK.

   

Sodafarl

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Anonymous
Not applicable

thank you .

   

the fifo is working now,but it is not stable.

   

Did you have this problem?

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New Contributor II

Hi,

   

Slave fifo works okay for me. You could check the timings of the FPGA control signals.

   

Sodafarl

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Anonymous
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yes,mine is fine now,thank for your help ..

   

best regard.

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Anonymous
Not applicable

hi.

   

  did you use the CyAPI.lib to write your program?or did you used the CyAPI.lib to get data from fx3 ?

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New Contributor II

Hi,

   

I used the Cypress Control Center application.

   

Sodafarl

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Anonymous
Not applicable

oh.I know.

   

I plan to write one,because I want to show the data.(it is a Image.)and, test the speed .

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Anonymous
Not applicable

                                    
sodafarl and 
                                               

jogn_li

hello!

   

   

  I'm puzzled with my FPGA codes,here is what i wrote ,i didn't know what my faults are ,can you tell me?

   

   

   

always @(posedge CLK)

   

 begin

   

  count<=count+5'b00001;

   

  if(count==5'b11111) count<=5'b11110;

   

 end

   

always @(posedge CLK)  //

   

   case(count)

   

    1:

   

      begin

   

       SLCS<=1;

   

       SLWR<=1;

   

       PKTEND<=1;

   

       A<=2'bzz;

   

       D<=16'bz;

   

      end

   

    3:SLCS<=0;

   

    4:A<=2'b00;

   

    6:SLWR<=0;

   

    7:

   

      begin

   

        data2usb=16'b0011000100110001; //

   

        D=data2usb;

   

      end

   

    9:

   

      begin

   

        data2usb=16'b0011000100110001; //

   

        D=data2usb;

   

      end

   

    11:

   

      begin

   

        data2usb=16'b0011000100110001; //

   

        D=data2usb;

   

      end

   

    13:

   

      begin

   

        data2usb=16'b0011000100110001; //

   

        D=data2usb;

   

      end

   

    15:

   

      begin

   

        data2usb=16'b0011000100110001; //

   

        D=data2usb;

   

        PKTEND=0;

   

      end  

   

    17:PKTEND<=1;

   

    18:SLWR<=1; 

   

    default:begin 

   

            end

   

   endcase

   

could you tell me what my problems are? thank you very much!

   

regards,

   

lint

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Anonymous
Not applicable

i'm a green hand,could you help me? the CLK is the FPGA system clk,i use it as my fifo xfer PCLK,is that OK? and i didn't change anything in the slave fifo example from the SDK1.0.1.

   

the follow is what i write today,i want to write to fx3 all the time,

   

   

always @(posedge CLK)

   

  begin

   

    PKTEND<=1;

   

    SLOE<=1;

   

    SLCS<=0;

   

    A<=2'b00;

   

   SLWR<=0;

   

  end

   

   

always @(posedge CLK)  //

   

 begin

   

  data2usb=16'b0011000100110001;

   

  D=data2usb;

   

 end

   

i can't find anything when i use the Bulk in button in the  USB Control Center,and i know the FLAG shows Not Full  .

   

regards,

   

lint

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New Contributor II

Hi,

   

You should be able to use your FPGA system clock for PCLK - what speed is it. Have you checked that the FPGA control signals are arriving at the FX3 and that there is no difference in the VIO voltage domains.  I am still using SDK verison 1.0.0, where did you download SDK 1.0.1.

   

Sodafarl

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Anonymous
Not applicable

 Sodafar1

   

hi,thank you for your reply,my FPGA system clock is 50MHz,the FPGA work on it and my PCLK is it too,is that OK? 

   

the SDK1.0.1 you can find it in this website,hope it won't take you much time to find it,

   

I don't quite get your point? you say the problem is my FPGA control signals make no difference to the FX3 because of  the VIO voltage domain ,but I can work asynchronous slave fifo well,so I thing my problem maybe stay at the PCLK or the timing sequence? maybe i didn't catch you point,i will check the VIO voltage first.

   

regards,

   

lint

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Anonymous
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sodafarl,

   

oh,i forget an important signal,i have solve my problem,a ha ,

   

thanks very much

   

regards,

   

lint

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Anonymous
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can you tell us what is your problem?

   

the important signal is ?

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Anonymous
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        i forget to configure one of my pins in my fpga.   
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