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USB Superspeed Peripherals

New Contributor

Hello

I'm Juyeol.

I plan to make the FPGA Configuration using GPIF master mode.
I have a question during fw coding, so please contact us.
Currently, I am using only the output value after deleting the input from the GPIF designer tool that has been uploaded(AN87216 Master mode).
Control Center provided by cypress, there are Control Endpoint and Bulk Out Endpoint. When I take an oscilloscope, data goes out from the Bulk Out Endpoint but not from the Control Endpoint, but I wonder if the two are different.

I think settings are same..

Thanks.

pastedImage_0.png

        if ((bTarget == CY_U3P_USB_TARGET_ENDPT) && (bRequest == CY_U3P_USB_SC_CLEAR_FEATURE)

                && (wValue == CY_U3P_USBX_FS_EP_HALT))

        {

            if ((wIndex == CY_FX_EP_PRODUCER) || (wIndex == CY_FX_EP_CONSUMER))

            {

                if (glIsApplnActive)

                {

                    CyU3PDmaChannelReset (&glChHandleBulkLpUtoP);

                    CyU3PUsbFlushEp(CY_FX_EP_PRODUCER);

                    CyU3PUsbFlushEp(CY_FX_EP_CONSUMER);

                    CyU3PUsbResetEp (CY_FX_EP_PRODUCER);

                    CyU3PUsbResetEp (CY_FX_EP_CONSUMER);

                    CyU3PDmaChannelSetXfer (&glChHandleBulkLpUtoP, CY_FX_DMA_TX_SIZE);

                    CyU3PUsbStall (wIndex, CyFalse, CyTrue);

                    isHandled = CyTrue;

                }

            }

        }

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1 Solution
Moderator
Moderator

Hello,


The thread has been answered in: CYUSB3KIT-003 PCLK voltage level?

The issue was with the 1.8V power domain and resolving it fulfilled the requirement.


Regards,

Yashwant

View solution in original post

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11 Replies
Moderator
Moderator

Hello Juyeol,

Can you please elaborate your application? Is it to configure FPGA with a bit file or is it to communicate with FPGA where FX3 acts as master and FPGA as a slave using the slaveFIFO interface?

Please clarify.

"Currently, I am using only the output value after deleting the input from the GPIF designer tool that has been uploaded(AN87216 Master mode)."

=> It is not advisable to delete the input values since the inputs in the AN87216 master SM are related to the availability of FLAGs and associated buffers for bulk data transfer. Also, the inputs/ FLAGs are used as a mechanism to implement flow control such that there is no data loss when transferring data between master and slave.

"Control Center provided by cypress, there are Control Endpoint and Bulk Out Endpoint. When I take an oscilloscope, data goes out from the Bulk Out Endpoint but not from the Control Endpoint, but I wonder if the two are different."

=> Can you please let me know how you were able to probe the control and bulk endpoints (where the oscilloscope leads were connected to the FX3)?

Also, control and bulk endpoints are not the same and have different functions associated with them.

To understand more about control and bulk endpoints and transfers, please read through the following links:

1.) USB 3.0 Specifications – SuperSpeed Data Flow Model - usbtips.com

2.) https://www.beyondlogic.org/usbnutshell/usb4.shtml

Generally, control endpoints are used for sending class-specific or vendor-specific commands which can be handled in the firmware but they cannot be used to transfer bulk data.

The reason for this error:997 is because the vendor command 0x00 is not being handled in the firmware.


Bulk endpoints are used to transfer bulk data between a host and a peripheral device.

Please elaborate on your target application so that I can understand it better.

Regards,

Yashwant

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New Contributor

OK. I read to your links and I understand.

And now I want to lower the p port clock speed, but the control is not working under 25mhz. What should I do?
I write come comment.

    /* Initialize the p-port block. */
    //pibClock.clkDiv = 4;  //100mhz
    pibClock.clkDiv = 16;   //25mhz
    //pibClock.clkDiv = 32;   //12.5mhz (bulk out failed)
    //pibClock.clkDiv = 64;   //6.25mhz (no clock out)

    pibClock.clkSrc = CY_U3P_SYS_CLK;  //400mhz

    //pibClock.clkDiv = 16;   //6.25mhz (no clock out)
    //pibClock.clkSrc = CY_U3P_SYS_CLK_BY_2; //25mhz

Please let me know I want 3mhz ~ 8mhz. how can i set??

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Moderator
Moderator

Hello,

Please refer to the following KBA: Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733

Set the DLL configurations for Ouput Clock < 80 MHz and try for setting the required frequency.

Regards,

Yashwant

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New Contributor

I need to Master mode GPIFII under 25mhz.

So you mean Table2 Synchronous Master.

pastedImage_0.png

But How can I set the CORE_PHASE ~ SLAVE_MODE?

This AN87216 Master mode sample code has just this one.

#define CY_FX3_PIB_DLL_CTRL_REG         (*(uvint32_t *)(0xe0010028))

#define CY_FX3_PIB_DLL_ENABLE           (0x00000001)                    /* Bit to enable the DLL. */
#define CY_FX3_PIB_DLL_HIGH_FREQ        (0x00000002)                    /* Set DLL into high freq (> 70 MHz) mode. */
#define CY_FX3_PIB_DLL_LOCK_STAT        (0x00000004)                    /* DLL lock status. */
#define CY_FX3_PIB_DLL_CORE_PHASE_POS   (4)                             /* Position of core clock phase field. */
#define CY_FX3_PIB_DLL_SYNC_PHASE_POS   (8)                             /* Position of sync clock phase field. */
#define CY_FX3_PIB_DLL_OP_PHASE_POS     (12)                            /* Position of output clock phase field. */
#define CY_FX3_PIB_DLL_RESET_N          (0x40000000)                    /* DLL reset request bit. */

static void


CyFxApplnSetPibDllParameters (
        CyBool_t isEnable,              /* Whether to enable the DLL. */
        uint8_t  corePhase,             /* Delay selection for the PIB core clock.
                                           Takes a value between 0 and 15, and applies a delay of
                                           (corePhase * 22.5 degrees) from the master clock. */
        uint8_t  syncPhase,             /* Delay selection for the data synchronizer clock used in async modes. */
        uint8_t  opPhase                /* Delay selection for the output clock driven by FX3. */
        )
{
    /* Disable DLL */
    CY_FX3_PIB_DLL_CTRL_REG &= ~(CY_FX3_PIB_DLL_ENABLE);
    CyU3PBusyWait (1);

    if (!isEnable)
        return;

    /* Configure and enable the DLL. */
    CY_FX3_PIB_DLL_CTRL_REG = (
            ((corePhase & 0x0F) << CY_FX3_PIB_DLL_CORE_PHASE_POS) |
            ((syncPhase & 0x0F) << CY_FX3_PIB_DLL_SYNC_PHASE_POS) |
            ((opPhase & 0x0F)   << CY_FX3_PIB_DLL_OP_PHASE_POS) |
            CY_FX3_PIB_DLL_HIGH_FREQ |
            CY_FX3_PIB_DLL_ENABLE
            );

    /* Reset the DLL */
    CY_FX3_PIB_DLL_CTRL_REG &= ~(CY_FX3_PIB_DLL_RESET_N);
    CyU3PBusyWait (1);

    /* Clear Reset */
    CY_FX3_PIB_DLL_CTRL_REG |= CY_FX3_PIB_DLL_RESET_N;
    CyU3PBusyWait (1);

    /* Wait for DLL to lock */
    while (!(CY_FX3_PIB_DLL_CTRL_REG & CY_FX3_PIB_DLL_LOCK_STAT));
}

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New Contributor

Is that right???

    CY_FX3_PIB_DLL_CTRL_REG = (

            ((corePhase & 0x0F) << CY_FX3_PIB_DLL_CORE_PHASE_POS) |

            ((syncPhase & 0x0F) << CY_FX3_PIB_DLL_SYNC_PHASE_POS) |

            ((opPhase & 0x0F)   << CY_FX3_PIB_DLL_OP_PHASE_POS) |

            CY_FX3_PIB_DLL_HIGH_FREQ |

            CY_FX3_PIB_DLL_ENABLE

            );

    --->

    CY_FX3_PIB_DLL_CTRL_REG = 0x388DBFF1;

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Moderator
Moderator

Hello Juyeol,

CY_FX3_PIB_DLL_CTRL_REG = (

((0xf & 0x0F) << CY_FX3_PIB_DLL_CORE_PHASE_POS) |

((0xf & 0x0F) << CY_FX3_PIB_DLL_SYNC_PHASE_POS) |

((opPhase & 0x0F) << CY_FX3_PIB_DLL_OP_PHASE_POS) |

(0x1 << 16) | // DLL_MODE -> SLAVE

(0x46 << 17) | // SLAVE_DELAY

(0x0 << 1) | // CY_FX3_PIB_DLL_HIGH_FREQ

(0x7 << 27) | // SLAVE_MODE

CY_FX3_PIB_DLL_ENABLE

);

Also, comment out this line in CyFxApplnSetPibDllParameters() (since Wait for DLL Lock is not needed):

    /* Wait for DLL to lock */

   // while (!(CY_FX3_PIB_DLL_CTRL_REG & CY_FX3_PIB_DLL_LOCK_STAT));

After setting the DLL as above, select the clkSrc and the clkDiv according to your clocking frequency.

Regards,
Yashwant

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New Contributor

Hello.

As I said, the test is in progress after setting it to 3.25mhz, but the clock rising doesn't seem to fit well.

And also I cotrol phase (CY_FX3_PIB_DLL_CORE_PHASE_POS, CY_FX3_PIB_DLL_SYNC_PHASE_POS, CY_FX3_PIB_DLL_OP_PHASE_POS) register the clock does not move even if the phase is moved(set the control register).

I want to match the rising edge to the data center (I want to push 180 degrees). How do I set it to move the clock phase?

I sent data aa/99/55/66. plz check the risng edge in the picture below.

Please let me know.

Thanks.

pastedImage_0.png

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Moderator
Moderator

Hello Juyeol,

In the CyFxApplnSetPibDllParameters (), please keep the values according to the values mentioned in table 2 from above (to be set as):
    CyFxApplnSetPibDllParameters (CyTrue, 15, 15, 11);

"And also I cotrol phase (CY_FX3_PIB_DLL_CORE_PHASE_POS, CY_FX3_PIB_DLL_SYNC_PHASE_POS, CY_FX3_PIB_DLL_OP_PHASE_POS) register the clock does not move even if the phase is moved(set the control register)."

=> Please don't change the values of the PHASE register ( CY_FX3_PIB_DLL_CORE_PHASE_POS, CY_FX3_PIB_DLL_SYNC_PHASE_POS, CY_FX3_PIB_DLL_OP_PHASE_POS ) as these are the position of respective values in the DLL register and shouldn't be changed.

"I want to match the rising edge to the data center (I want to push 180 degrees). How do I set it to move the clock phase?"

=>From this, I understand that you want to change the clock polarity (Please correct me if that's not the requirement).

To do this, open the master_read_write_sync.cyfx in the project, and change the "Active Clock Edge" to 'Negative' (from Positive) and build and add newly generated "cyfxgpif_syncsf.h" to project and perform a clean build and try to probe the setup again.

Regards,

Yashwant

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New Contributor

Hello Yashwant,

As shown in the picture below, values that look like garbage values keep appearing between data and data. Is this normal?
When we receive the data, the data appears randomly twice, but I think it is because of this, so please let me know how to remove that garbage data.

pastedImage_4.png

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Moderator
Moderator

Hello,

Can you please share the pib config structure that you are using currently to generate the above waveforms?

Please share it so that I can try to reproduce the issue on my end.

Regards,
Yashwant

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Moderator
Moderator

Hello,


The thread has been answered in: CYUSB3KIT-003 PCLK voltage level?

The issue was with the 1.8V power domain and resolving it fulfilled the requirement.


Regards,

Yashwant

View solution in original post

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