Hello
I'm Juyeol.
I plan to make the FPGA Configuration using GPIF master mode.
I have a question during fw coding, so please contact us.
Currently, I am using only the output value after deleting the input from the GPIF designer tool that has been uploaded(AN87216 Master mode).
Control Center provided by cypress, there are Control Endpoint and Bulk Out Endpoint. When I take an oscilloscope, data goes out from the Bulk Out Endpoint but not from the Control Endpoint, but I wonder if the two are different.
I think settings are same..
Thanks.
if ((bTarget == CY_U3P_USB_TARGET_ENDPT) && (bRequest == CY_U3P_USB_SC_CLEAR_FEATURE)
&& (wValue == CY_U3P_USBX_FS_EP_HALT))
{
if ((wIndex == CY_FX_EP_PRODUCER) || (wIndex == CY_FX_EP_CONSUMER))
{
if (glIsApplnActive)
{
CyU3PDmaChannelReset (&glChHandleBulkLpUtoP);
CyU3PUsbFlushEp(CY_FX_EP_PRODUCER);
CyU3PUsbFlushEp(CY_FX_EP_CONSUMER);
CyU3PUsbResetEp (CY_FX_EP_PRODUCER);
CyU3PUsbResetEp (CY_FX_EP_CONSUMER);
CyU3PDmaChannelSetXfer (&glChHandleBulkLpUtoP, CY_FX_DMA_TX_SIZE);
CyU3PUsbStall (wIndex, CyFalse, CyTrue);
isHandled = CyTrue;
}
}
}
I need to Master mode GPIFII under 25mhz.
So you mean Table2 Synchronous Master.
But How can I set the CORE_PHASE ~ SLAVE_MODE?
This AN87216 Master mode sample code has just this one.
#define CY_FX3_PIB_DLL_CTRL_REG (*(uvint32_t *)(0xe0010028))
#define CY_FX3_PIB_DLL_ENABLE (0x00000001) /* Bit to enable the DLL. */
#define CY_FX3_PIB_DLL_HIGH_FREQ (0x00000002) /* Set DLL into high freq (> 70 MHz) mode. */
#define CY_FX3_PIB_DLL_LOCK_STAT (0x00000004) /* DLL lock status. */
#define CY_FX3_PIB_DLL_CORE_PHASE_POS (4) /* Position of core clock phase field. */
#define CY_FX3_PIB_DLL_SYNC_PHASE_POS (8) /* Position of sync clock phase field. */
#define CY_FX3_PIB_DLL_OP_PHASE_POS (12) /* Position of output clock phase field. */
#define CY_FX3_PIB_DLL_RESET_N (0x40000000) /* DLL reset request bit. */
static void
CyFxApplnSetPibDllParameters (
CyBool_t isEnable, /* Whether to enable the DLL. */
uint8_t corePhase, /* Delay selection for the PIB core clock.
Takes a value between 0 and 15, and applies a delay of
(corePhase * 22.5 degrees) from the master clock. */
uint8_t syncPhase, /* Delay selection for the data synchronizer clock used in async modes. */
uint8_t opPhase /* Delay selection for the output clock driven by FX3. */
)
{
/* Disable DLL */
CY_FX3_PIB_DLL_CTRL_REG &= ~(CY_FX3_PIB_DLL_ENABLE);
CyU3PBusyWait (1);
if (!isEnable)
return;
/* Configure and enable the DLL. */
CY_FX3_PIB_DLL_CTRL_REG = (
((corePhase & 0x0F) << CY_FX3_PIB_DLL_CORE_PHASE_POS) |
((syncPhase & 0x0F) << CY_FX3_PIB_DLL_SYNC_PHASE_POS) |
((opPhase & 0x0F) << CY_FX3_PIB_DLL_OP_PHASE_POS) |
CY_FX3_PIB_DLL_HIGH_FREQ |
CY_FX3_PIB_DLL_ENABLE
);
/* Reset the DLL */
CY_FX3_PIB_DLL_CTRL_REG &= ~(CY_FX3_PIB_DLL_RESET_N);
CyU3PBusyWait (1);
/* Clear Reset */
CY_FX3_PIB_DLL_CTRL_REG |= CY_FX3_PIB_DLL_RESET_N;
CyU3PBusyWait (1);
/* Wait for DLL to lock */
while (!(CY_FX3_PIB_DLL_CTRL_REG & CY_FX3_PIB_DLL_LOCK_STAT));
}
Hello.
As I said, the test is in progress after setting it to 3.25mhz, but the clock rising doesn't seem to fit well.
And also I cotrol phase (CY_FX3_PIB_DLL_CORE_PHASE_POS, CY_FX3_PIB_DLL_SYNC_PHASE_POS, CY_FX3_PIB_DLL_OP_PHASE_POS) register the clock does not move even if the phase is moved(set the control register).
Hello Yashwant,
As shown in the picture below, values that look like garbage values keep appearing between data and data. Is this normal?
When we receive the data, the data appears randomly twice, but I think it is because of this, so please let me know how to remove that garbage data.
