I aksed this question through a case also. Can anyone help me?
How to get the socket id for the P port for U to P or P to U transfer? What is the basis of selecting CY_U3P_PIB_SOCKET_0 and CY_U3P_PIB_SOCKET_3 in SlaveFifoAsync example?
We are likely to use 32 bits async slave fifo interface. We will have 2 IN and 2 OUT endpoints. e.g. -
2 - OUT
4 - OUT
What will be the "prodSktId" and "consSktId" for 4 DMA channels?
2 - OUT , prodSktId = CY_U3P_UIB_SOCKET_PROD_2 , consSktId = ?
4 - OUT, prodSktId = CY_U3P_UIB_SOCKET_PROD_4 , consSktId = ?
86 - IN, prodSktId = ? , consSktId = CY_U3P_UIB_SOCKET_CONS_6
88 - IN, prodSktId = ? , consSktId = CY_U3P_UIB_SOCKET_CONS_8
Socket 0 to 15 are bi-directional and the rest can only be producer sockets. There is nothing specific behind the reason for selection of socket 0 or socket 3. socket 1 or 2 etc can also be used.
The restriction here is that it has to match the GPIF descriptor. We've designed it with socket 0 and 3 in the example. That is all.
OK Thanks this clarifies.
How does the thread map with the socket? Lines A1:A0 point to the thread. Can you please tell me how this mapping is controlled in firmware?
As per application note AN65974 -
EZ-USB FX3 provides up to four physical threads for data transfer over the GPIF II. At a time, any one socket may be mapped to a thread. The sockets that are to be used must be mapped to a thread. This mapping is done by EZ-USB FX3 firmware. For example, suppose socket 2 is mapped to thread 0 and socket 3 is mapped to thread 1.
Note that the address signals A0:A1 on the interface indicate the thread to be accessed. FX3’s DMA fabric then routes the data to the socket mapped to that thread. Therefore, in this example, when A0:A1 = 0, thread 0 is accessed, and any data that is transferred over thread 0, will be routed to socket 2. Similarly, when A0:A1 = 1, data is transferred in and out of socket 3
I looked at the topic and the file gpif_regs.h. You have written -
"The 4 registers CY_U3P_PIB_GPIF_THREAD_CONFIG_ADDRESS map one of the 32 PIB sockets to the 4 physical threads of the GPIF. This is coded in the 5 least significant bits. So the SyncSlaveFIFO firmware example uses thread 0 and 3, as the 4 threads are mapped to the PIB sockets 0 to 3."
WHat is the basis of - "This is coded in the 5 least significant bits" ? Do you have any details of the registers ? In the file I see only -
#define CY_U3P_PIB_GPIF_THREAD_CONFIG_ADDRESS(n) (0xe00140fc + ((n) * (0x0004)))
Can someone from Cypress confirm the statement from Chris? I think at this stage this is sufficient for me.
In the lines below the Register address you can find the following comment:
Active Socket Number for this thread.
Can be written by software for fixed socket assignment.
Can be modified by h/w as result of PP_DMA_XFER accesses
Can be modified by h/w as result of alpha 'sample AIN'
#define CY_U3P_GPIF_THREAD_SOCK_MASK (0x0000001f) /* <0:4> RW:RW:0:Yes */
#define CY_U3P_GPIF_THREAD_SOCK_POS (0)
So I think, the socket number has to be written in the last 5 bits....in the example the sockets 0...3 are used.
>> The restriction here is that it has to match the GPIF descriptor. We've designed it with socket 0 and 3 in the example.
How to set (multiple)socket id in GPIF II designer? I'm also trying to follow Chris's solution, but can not really catch his idea. It seems hard for me to make the CY_U3P_DMA_TYPE_MANUAL_MANY_TO_ONE work. Can you point me a way?