I'm working on a Enclustra KX1 board, trying to write from the FPGA to GPIF2. Filling one buffer which according to spec should be transfered to the IN endpoint. The Cypress device is EZ-USB FX3. I do not have exact specifications of the firmware of the fx3 but it should according to their support be a bog-standard implementation of slfifosync from the SDK.
I can't quite get the interface to work, soo I was hoping I could get some help 🙂
I've created a simple module to write to the slaveFIFO (see StreamIN/StreamINCore).
StreamIN is a wrapper setting all the constants, and connecting some LEDS for debugging.
StreamINCore does the actual writing to the bus.
I am able to write to the FX3 and see FLAGA be asserted. I'm guessing FLAGA means there's data to read, and FLAGB means it is not full. (FLAGB=0 => Buffer=Full). ( I can write a total of 4*512 bytes to the FX3 before OUT buffer is full ).
I find the examples from Cypress hard to use, and does not seem to work for me. (See example: slfifosync.png)
Here they simply wait for FLAGB to go low as an indication of buffer being full.
In the(Designing with EZ-USB SlaveFifo) documentation this photo (write_seq.png) describes a write sequence, this is conflicting with the example. The example simply hardwires PKTEND although performing burst transfers. (Since waiting for FLAGB might go over several cycles). In my case I cannot see anything happening to FLAGB, thus it continues to write for eternity.
So how do I play the GPIF interface, or what am I doing wrong?
(SystemVerilog files are saved as *.sv.txt to be able to upload)
Thanks in advance!
Eirik, I see that you mentioned that you tried the example firmware from the SDK. Did you try the example project along with the application note? I am attaching the link to AN65974, you can find a pdf which will explain you most of the stuff related to the slave fifo implementation and also you can download an working and well tested example project from the link:
There is no predefined meaning of FLAG-A, it depends on what you have set it in the GPIF firmware. If it is a ready flag- then it will show is the buffers in DMA are ready to be read/written to. It will indicate that the buffers are not ready, when there is a transition of the active buffer (changing from one buffer to the next-when the buffer fills). If the flag is a water-mark type, then it will show the status reflecting if the buffer is about to get filled (or about to get emptied).
Please go through the application note once, then we can discuss further.
Yes, I've tried to kinda do the same as the StreamerIN example from AN65974. It looks a lot like the slfifosync example, (just waiting for the flag to be 1'b0 to stop putting data every cycle.
It seems to me that it should be possible to start the transfer once the flag is 1'b1. The only thing I've done different is that the example design has a lot of delay states in different levels of the hierarchy( a bit confusing). I'm guessing the delays have to do with the flag being configured as "almost full" instead of "full", so you can in fact squeeze out those one/two last bytes. At the moment they do not matter to me, but I'd like to be able just transfer something.
The write_seq attachment from the first post is from AN65974, showing a write sequence. It is conflicting with the implementation (both slfifosync and AN65974 example) in that it uses the PKTEND for burst transfers, examples do not.
I've also tried to only transfer 1 packet at a time, but I couldn't read the buffer that time either. ( It was just a loop trough the state machine if FLAG=1)
even i have problems regarding flag a and b in streamin mode??and write signals??i am not getting where is the problem ??is it from fpga side r fx3 side ????flags are not getting updated??but i am recieving 50% accepted datd from fpga-->fx3s-->pc through usb..please help me