Help with slave fifo sync source code

MoLa_3842091 · ‎Jul 24, 2019

Thanks Srinath S for your previous reply, I wished to continue discussion but it has been locked,

Referring to our previous discussion help with slavefifo sync source code I have chosen to use only the DMA ready flags for each thread used in your application omitting the watermark flags and I have implemented it. It worked with me but I still have an issue with the looped back data, it adds 4 bytes of value zero after each 8 bytes. The following is screen shot from USB Control Center showing the issue that is mentioned. I also attached verilog file "slaveFIFO2b_loopback.v" in case you would like to see the changes that I have made, I mainly omitted the watermark flags and updated the "LoopBack mode state machine combo". So what do you think is going wrong?

SrinathS_16 · ‎Aug 08, 2019

Hello,

Please note that FLAGA HIGH indicates that the buffer is not ready to accept or produce data and FLAGA LOW indicates that the buffer is ready to accept of produce data.

In the screenshot that you have shared, initially, thread 0 is addressed (A[1:0] - 0x00). FX3 samples this address lines and then incurs a 3-cycle latency to indicate the state of flag on the FLAGA pin. Hence, the FLAGA is initially de-asserted and is asserted only after 3 clock cycles to indicate that the buffers for socket of thread 1 is free and can be filled with data.

But, then, the address pins are modified to A[1:0] - 0x03 to select thread 3. This again incurs 3 clock cycles to indicate the valid state of socket associated with thread 3.

Please refer to the section 8.2 of the AN65974 document.

Best regards,

Srinath S

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Help with slave fifo sync source code

Help with slave fifo sync source code

Re: Help with slave fifo sync source code