Jul 04, 2016
12:57 AM
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Jul 04, 2016
12:57 AM
Hi,
I am using GPIF interface as a synchronous slave FIFO input. The transmission is initiated by the FX3 by pulsing a GPIO line. However the trigger signal must be synchronized to the GPIF clock rather than the FX3s main clock in this design. How can I ensure the IO buffer of a spare GPIF CTLx pin is still using the GPIF clock source after I override it to use it as a simple IO within the firmware?
Cheers,
Helmut
2 Replies