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I am using GPIF interface as a synchronous slave FIFO input. The transmission is initiated by the FX3 by pulsing a GPIO line. However the trigger signal must be synchronized to the GPIF clock rather than the FX3s main clock in this design. How can I ensure the IO buffer of a spare GPIF CTLx pin is still using the GPIF clock source after I override it to use it as a simple IO within the firmware?
Thanks Nishant, this what I ended up doing: I added an additional state transition to an idle state which is triggered by the Firmware trigger. While in the firmware triggered state the GPIO output signal is asserted. Now I can produce a GPIF clock synchronous trigger while the GPIF is in this idle state. However I will have to be able to assert this trigger signal independent of the state, as the next measurement should be triggered during transmission of the current measurement. Is there a way to create a second independent state machine for forwarding the firmware trigger, or some neat way to implement this rather than having a firmware trigger asserted copy of each state?