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USB Superspeed Peripherals

Marc_O
New Contributor II

Hi,

I'm working on a FX3 -> FPGA (Xilinx Artix 7) interface using the GPIFII interface.

I went through all the AN65974 document (a wonderfull piece:), but unfortunately, I was able to only make the Slave FIFO Write Sequence. I tried the loopback part without any success.

I had to modified it a bit since my system is only using 2 flags, therefore, I modified the GPIF to have current flag for A and B.

Marc_O_3-1622696268719.png

The write sequence went smooth and I was able to read data from the ControlCenter and retrieve a simple counter value. Very basic here.

I wanted to do the same with the read sequence but it never worked. I'm able to send data and see with Vivado debugger that the flag was raised. But no data get on the bus. Here is what I sent with the ControlCenter:

Marc_O_0-1622695715834.png

Once the data is sent, the flag is trigger in the FPGA and I get the following waves:

Marc_O_1-1622695768804.png

As you can see, the flaga was raised when I clicked on Transfer Data-Out but nothing appears on the bus. Note that the "q_data_in_use" is a clock signal that sample the value of the data bus (32 bits). I would expect to see my "ABCD_EF" appears at one time.

Also, since I only send 3 bytes, I would have expect the flaga to return to 0 very quicly. but as you can see in the waves, "slrd_n", "slrd_n" never go up and therefore, according to the timing diagram of the AN65974  document, I'm still in a burst read. Maybe I'm misunderstanding the flags here but I though that once my 3 bytes are read, the socket should be empty and the flag going down ('0'). Therefore, I could stop my read burst.

 

As of now, I decided to go to the very basic in order to debug what was going on. I did a new GPIF state machine to only support the read sequence:

Marc_O_2-1622696094789.png

SLWR&!SLCS&!SLRD&!SLOE  -> to go to read

SLRD|SLCS|SLOE -> return to IDLE

 

I wanted to avoid having a dead state so with this, there is only one possibiliy!

 

Note on my setup:
I'm using the AN65974 FX3 firmware with only the header file of the GPIFII which has changed as explained earlier.

I have also defined the "LOOPBACK_SHRT_ZLP" and undefined the "MANUAL".

I'm attaching the files of the FX3 firmware with the heater file of the GPIF.

 

I hope you can help me with that issue, it is really a big stopper for our development as we need to be able to both read and write to the host.

Thanks a lot in advance.

Marc-Olivier

1 Solution
Marc_O
New Contributor II

Hi AliAsgar,

Sorry for the delay. I finally found after a lot of tests that some signals on the board I'm working on are not driven by the FX3. We will investigate that, there might be isssues on our board.

Anyhow, I was able to make it work by having the FX3 being the master and the FPGA being the slave since with that configuration, I need less pins so I can work with the working remaining pins. I am now able to do both RX and TX without problem... though there seems to be a lot of latency.

I'm curious, why does the DR_GPIO has a 3 clock latency?

I would also have another question. In my current design, with the FX3 acting as a master and my FPGA acting as the slave, the FPGA still provide the clock to the FX3. I was wondering if I need to phase shift the clock at 180° that I give to the FX3.

I ended up making the active clock edge "negative" in the GPIF because otherwise, I was getting unstable data when sending data to the FPGA. I read the AN87216 but I could not find a place where they specified the clock.

Thanks

 

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AliAsgar
Moderator
Moderator

Hi Marc-Olivier,

Could you share with us the complete project (including the GPIF project) you are using originally, for both writing and reading.

Please verify the timing diagrams with Figure 3 and Figure 6 of AN65974.

Best Regards,
AliAsgar

 

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Marc_O
New Contributor II

Hi AliAsgar,

Thanks for you quick response. Here are the 2 projects.

For the flags, I have:
- flaga : dedicated to thread 0

- flagb : dedicated to thread 1

I looked a lot at the Figure 3, I'm quite sure I implemented the same as you can see in this waveform from the FPGA. Here, I do only 1 read (1 clock cycle) after the flag goes up compare with the other one in my post where I maintain the read burst. But I do it repeatly if the flagb is still on.

Marc_O_0-1622723036286.png

I'm still sending x"ABCD_EF", and still, I'm not sampling any data. And moreover, the flagb never go down even though I suppose I read the data...

Hopefully you will be able to see what I'm doing wrong.

Thanks

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AliAsgar
Moderator
Moderator

Hi Marc-Olivier,

1. Please refer to this KBA https://community.cypress.com/t5/Knowledge-Base-Articles/Debugging-when-DMA-Flags-do-not-Work-as-Exp..., especially point no. 4.

2. Could you let us know if there any changes made in the state machine verilog script at the FPGA side, apart from the one we have shared in AN65974.

3. Could you program FX3 using the image file built using the project I have attached here and send the debug logs?

Best Regards,
AliAsgar

 

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Marc_O
New Contributor II

Hi AliAsgar,

Sorry for the delay. I finally found after a lot of tests that some signals on the board I'm working on are not driven by the FX3. We will investigate that, there might be isssues on our board.

Anyhow, I was able to make it work by having the FX3 being the master and the FPGA being the slave since with that configuration, I need less pins so I can work with the working remaining pins. I am now able to do both RX and TX without problem... though there seems to be a lot of latency.

I'm curious, why does the DR_GPIO has a 3 clock latency?

I would also have another question. In my current design, with the FX3 acting as a master and my FPGA acting as the slave, the FPGA still provide the clock to the FX3. I was wondering if I need to phase shift the clock at 180° that I give to the FX3.

I ended up making the active clock edge "negative" in the GPIF because otherwise, I was getting unstable data when sending data to the FPGA. I read the AN87216 but I could not find a place where they specified the clock.

Thanks

 

View solution in original post

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AliAsgar
Moderator
Moderator

Hi Marc-Olivier,

DR_GPIO has 2 clock latency for early mode and 3 clock latency for delayed mode. This is by design.

Why do you think you need to do 180 degree phase shift for the clock?

Best Regards,
AliAsgar

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