GPIFII - Dual Sockets don’t follow order of socket linked list

[HuYa_4249091]

Hi, I've referred AN75779 doc to accomplish that for our project.

Now, we want to change the transmission mechanism:

1. FPGA will send out 2 type of data: image & info to FX3
2. image data uses dual socket & info data use single socket to receive
3. Use sw_pin to determine the type of the next incoming data
4. Each HREF may receives different type of data(ex: HREF1 – image, HREF2 – info, HREF3 – image…)
5. FPGA designs that each HREF data length is equal as the DMA buffer size(all are 8k)

Dummy state machine:

According to Getting Started doc, I've understood the mechanism for dual sockets yield:

The normal step behavior which use dual socket should like:

However, now, each HREF may receive different type of data. I worry it may cause Socket Linked List  conflict...

Ex: HREF1 – image, HREF2 – info, HREF3 – image, HREF4 – image

My inference step behavior:

In the step 1, load the DMA Descriptor1 on socket1(thread1). However, the next image data is received by socket0, not the expected socket1.

Q1: Will it cause the conflict as the following fig and cause crash for USB transmission?

Q2: If the answer for Q1 is yes. Can I use the commands in FW to reset Socket Linked List to avoid the conflict?CyU3PDmaMultiChannelReset(&glChHandleSlFifoPtoU);
CyU3PDmaMultiChannelSetXfer(&glChHandleSlFifoPtoU, 0, 0);
CyU3PDmaMultiChannelSetXfer(&glChHandleSlFifoPtoU, 0, 1); 

Thanks for your patience to read it. Any help will be highly appreciated!