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USB Superspeed Peripherals

HuYa_4249091
Contributor

Hi, there are two GPIF threads which are similar to AN75779's mechanism in my project, and it can transfer image data smoothly.
Now, I’m researching GPIFII’s "DMA ready" ability. Therefore,  I’ve TWO questions for that.

Q1: In the GPIFII - Interface Definition tab, I set the DMA flags: 2

DMA flags.jpg

And my flag setting

Flag Settings.JPG

After this setting, the corresponding pin will output HIGH while the DMA thread X is ready, and output LOW while the DMA thread X is preparing?

Q2: If I just want to use "DMA ready" ability, I can use FW api - CyU3PGpifOutputConfigure() to TOTALLY REPLACE Q1’s GPIFII setting?

Why I ask that? Because I found if I programmed the code as

CyU3PGpifOutputConfigure.JPG

The "DMA ready" pins still output the signal, even though I DON'T set the Q1’s setting.

waveform.jpg

Any help will be highly appreciated!

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello,

Please find my comments for your questions below:

1. The setting shown in the snapshot will not yield " the corresponding pin will output HIGH while the DMA thread X is ready, and output LOW while the DMA thread X is preparing". For obtaining this, you can set initial value to low and polarity to Active Low. With this setting, the corresponding flag will go high, when there is data in the DMA buffer associated with the P Port socket for external device to read/when there is space in the DMA buffer associated with P Port socket for external device to write. That is, the flag will stay high when the DMA thread is ready and low when the DMA thread is not ready.

But, there is a latency for the ready flag to have a transition from HIGH to LOW when the DMA buffers associated with the socket is full/empty (depending on the operation). Please refer to Table 4 of AN65974 which documents these latencies for slave fifo interface. The link to AN65974 is given below:
https://www.cypress.com/file/136056/download

This means that even when the DMA buffer is full/empty, the flag status may not change until the mentioned clock cycles are elapsed. Due to this, we do not recommend to use a ready flag for terminating a transfer. Ready flag should only be monitored for starting transfers. For terminating the transfers, watermark flag should be used.  Please refer to AN65974 to understand more about watermark flags.

2. Yes, this API can be used as a replacement for the setting described in Q1. This is already mentioned in the following thread:
https://community.cypress.com/t5/USB-Superspeed-Peripherals/CYU3P-GPIF-OP-THR0-READY/m-p/89519

But, please refer to the FX3 API guide which mentions that any GPIF configuration API calls such as CyU3PGpifLoad or CyU3PGpifRegisterConfig can override this configuration. So, please use this API carefully. In addition to this, the last parameter of the API CyU3PGpifOutputConfigure() (isActiveLow) is used for setting the polarity of the flag for this use case. If this parameter is set to CyTrue, then it indicates that the polarity of the flag will be Active Low. If it is set as CyFalse, then it indicates that the polarity of the flag will be Active High.

Again, please note that it is not recommended to use ready flags alone for starting and terminating transfers. For starting a transfer, ready flag needs to be used and for terminating the transfer, watermark flag needs to be used.

Best Regards,
Jayakrishna

View solution in original post

5 Replies
JayakrishnaT_76
Moderator
Moderator

Hello,

Please find my comments for your questions below:

1. The setting shown in the snapshot will not yield " the corresponding pin will output HIGH while the DMA thread X is ready, and output LOW while the DMA thread X is preparing". For obtaining this, you can set initial value to low and polarity to Active Low. With this setting, the corresponding flag will go high, when there is data in the DMA buffer associated with the P Port socket for external device to read/when there is space in the DMA buffer associated with P Port socket for external device to write. That is, the flag will stay high when the DMA thread is ready and low when the DMA thread is not ready.

But, there is a latency for the ready flag to have a transition from HIGH to LOW when the DMA buffers associated with the socket is full/empty (depending on the operation). Please refer to Table 4 of AN65974 which documents these latencies for slave fifo interface. The link to AN65974 is given below:
https://www.cypress.com/file/136056/download

This means that even when the DMA buffer is full/empty, the flag status may not change until the mentioned clock cycles are elapsed. Due to this, we do not recommend to use a ready flag for terminating a transfer. Ready flag should only be monitored for starting transfers. For terminating the transfers, watermark flag should be used.  Please refer to AN65974 to understand more about watermark flags.

2. Yes, this API can be used as a replacement for the setting described in Q1. This is already mentioned in the following thread:
https://community.cypress.com/t5/USB-Superspeed-Peripherals/CYU3P-GPIF-OP-THR0-READY/m-p/89519

But, please refer to the FX3 API guide which mentions that any GPIF configuration API calls such as CyU3PGpifLoad or CyU3PGpifRegisterConfig can override this configuration. So, please use this API carefully. In addition to this, the last parameter of the API CyU3PGpifOutputConfigure() (isActiveLow) is used for setting the polarity of the flag for this use case. If this parameter is set to CyTrue, then it indicates that the polarity of the flag will be Active Low. If it is set as CyFalse, then it indicates that the polarity of the flag will be Active High.

Again, please note that it is not recommended to use ready flags alone for starting and terminating transfers. For starting a transfer, ready flag needs to be used and for terminating the transfer, watermark flag needs to be used.

Best Regards,
Jayakrishna

View solution in original post

HuYa_4249091
Contributor

Dear Jayakrishna:

Thanks for your reply & explanation!

Therefore, for the CyU3PGpifOutputConfigure(11, CYU3P_GPIF_OP_THR0_READY, isActiveLow=True)
"isActiveLow = True" means:
DMA thread is ready: output HIGH
DMA thread is NOT ready: output LOW; The DMA buffer is full, so DMA thread needs some time to load  next DMA buffer descriptor -> the load activity like ACTIVE

Thank you!

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JayakrishnaT_76
Moderator
Moderator

Hello,

Can you please elaborate this statement "the load activity like ACTIVE" in your previous response so that we can understand it better?

Also, as mentioned in my previous reply, there is a latency between the DMA buffer getting full and the ready flag undergoing a transition from HIGH to LOW. Please refer to Table 4 of AN65974 which documents these latencies for slave fifo interface. The link to AN65974 is given below:
https://www.cypress.com/file/136056/download

Best Regards,
Jayakrishna
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HuYa_4249091
Contributor

Dear Jayakrishna:

Thanks for your reply! Sorry for the not completed description.


Can you please elaborate this statement "the load activity like ACTIVE" in your previous response so that we can understand it better?


We send out the image data by FPGA, and it always send 8k bytes data in each HREF.
So I set the DMA buffer size to 8k to match that.

While I set the commands in FW:
CyU3PGpifOutputConfigure(11, CYU3P_GPIF_OP_THR0_READY, CyTrue);
CyU3PGpifOutputConfigure(6, CYU3P_GPIF_OP_THR1_READY, CyTrue);

And observe the waveform:
waveform detail.jpg
We found that the th0_rdy & th1_rdy usually keep in high.
While thread0 DMA buffer is full(HREF become to low), the th0_rdy become low for a few time.
And then, the thread1 DMA buffer is used to receive the next HREF data...

According to the behavior, so I guess that the thX_rdy becomes to low while it's preparing(not ready).
Is my understanding not right?

 

Also, as mentioned in my previous reply, there is a latency between the DMA buffer getting full and the ready flag undergoing a transition from HIGH to LOW. 

Thank you for your reminder! I know it will cause some latency now.
However, in our case, the PC application receiver may block to receive data.
I think I need the DMA ready signal to judge is there available DMA buffer in FX3. If only there is available DMA buffer in FX3, the  FPGA sends the next image data.

Thank you!

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JayakrishnaT_76
Moderator
Moderator

Hello,

Please find my comments on your previous reply below:

According to the behavior, so I guess that the thX_rdy becomes to low while it's preparing(not ready).
Is my understanding not right?

>> Yes, your understanding is correct. But as mentioned in my previous reply, even after the DMA buffer is full, there is a latency for the flag status to change. This means that the buffer would be full even before the status of the ready flag change.  The ready flag associated with the socket will again go high when a DMA buffer is ready to store the data sampled by that socket.

Best Regards,
Jayakrishna