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I have a state machine transferring GPIF to USB. The transition from my wait state is defined as DMA_RDY_THx&!BUSY where busy is a pin on the external interface to indicate if there is data ready, I then read this data until WM, read the rest of the packet and then transfer back to the wait state, the usb packet is sent.
If I get back to the wait state and there is no data ready on my external interface then it waits a while and transitions when !BUSY and everything works fine. If it gets back to the wait state and the interface is already !BUSY then some data is lost (transferred over the GPIF but not transferred over the USB). The only conclusion I can draw from this is that the DMA_RDY and DMA _WM flags are not correct when I am in my wait state? AN65974 indicates that there is a 3 cycle latency of the DMA _RDY flag but insertting a dummy state with considerably more wait than this does not fix the problem. This also seems to be true if I do a commit of a shorter packet and then transfer to the wait state.
I can only think that this might be that the DMA flags are not valid during DMA buffer switching? Is there a way that I can detect the buffers are switching from my state machine?