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The KBA refers to configuring the DLL block of FX3 (based on desired output PCLK).
The DLL block is configured in the firmware using CyFxApplnSetPibDllParameters(). The configuration is based on output PCLK desired which is mentioned in Table 2 of the above mentioned KBA.
The Output PCLK frequency is based on the pibClock.clkDiv parameter. If the value of clkDiv is 4 or 5 and if the clock_source is SYS_CLK, then Output PCLK >= 80MHz and if value of clkDiv is greater than 5, Output PCLK < 80MHz and the values of the DLL parameters need to be updated accordingly from the table.
Please find the attached configuration shown in the images for PCLK<80MHz