cancel
Showing results for 
Search instead for 
Did you mean: 

USB Superspeed Peripherals

JaYe_3798301
New Contributor

Hi all,

I am now trying to get the GPIF II of my Fx3s working.

So I would like to try to run the AN82716 example first.

I would need to modify the GPIF II data bus from 32-bit to 16-bit since Fx3s only supports 16-bit data bus.

So I need the GPIF II source project of this example, both the master and slave.

I did found the cyfx file, but when I try to open it in the GPIF II designer, I got the following error.

Error: prj.M00007: Project "C:\Users\hsuan\Documents\GPIF II Designer\master_read_write_sync.cydsn\master_read_write_sync.cyfx" load failed. Error occurred while loading project documents.

0 Likes
Reply
1 Solution
YashwantK_46
Moderator
Moderator

Hi Jay,

Please refer to KBA attached : Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733

The KBA refers to configuring the DLL block of FX3 (based on desired output PCLK).

The DLL block is configured in the firmware using CyFxApplnSetPibDllParameters(). The configuration is based on output PCLK desired which is mentioned in Table 2 of the above mentioned KBA.

The Output PCLK frequency is based on the pibClock.clkDiv parameter. If the value of clkDiv is 4 or 5 and if the clock_source is SYS_CLK, then Output PCLK >= 80MHz  and if value of clkDiv is greater than 5, Output PCLK < 80MHz and the values of the DLL parameters need to be updated accordingly from the table.

Please find the attached configuration shown in the images for PCLK<80MHz

Regards,

Yashwant

View solution in original post

0 Likes
Reply
12 Replies
Hemanth
Moderator
Moderator

Hi,

Please check if there is a folder named 'projectfiles' in the directory where .cyfx file is present.

Also check whether gpif2model.xml, gpif2timingsimulation.xml and gpif2view.xml are present in 'projectfiles' directory.

If the folder with the above mentioned files are not present please re-download the AppNote project and verify.

Regards,

Hemanth

Hemanth
0 Likes
Reply
JaYe_3798301
New Contributor

Hi Hemanth,

Thanks for the prompt response.

I found the GPIF design files after re-download the zip file.

Tnank you.

Two more question:

1. How could I modify the GPIF II clock frequency in the Master side?

2. I found one definition in cyfxbulklpauto.h showing the selection between 16-bit and 32-bit data bus

    Is there any thing need to be changed to run the example in 16-bit data mode?

/* 16/32 bit GPIF Configuration select */

/* Set CY_FX_MA_GPIF_16_32BIT_CONF_SELECT = 0 for 16 bit GPIF data bus.

* Set CY_FX_MA_GPIF_16_32BIT_CONF_SELECT = 1 for 32 bit GPIF data bus.

*/

#define CY_FX_GPIF_16_32BIT_CONF_SELECT (1)

Thanks a lot.

Jay

0 Likes
Reply
YashwantK_46
Moderator
Moderator

Hi Jay,

1. The clock frequency of GPIF (PCLK) can be changed by using the CyU3PPibInit() API by changing the CyU3PPibClock_t paramater. In CyU3PPibClock_t, CyU3PSysClockSrc_t clkSrc is used to select the clock source frequency supplied ( derived from the SYS_CLK) and uint16_t clkDiv parameter defines the factor by which the frequency is to be divided (min-2 to max-1024).

Make sure that the PCLK does not exceed 100MHz.

2. To run the example in 16-bit mode, the following change to #define CY_FX_GPIF_16_32BIT_CONF_SELECT (0) is to be done.

  1. /* 16/32 bit GPIF Configuration select */ 
  2. /* Set CY_FX_MA_GPIF_16_32BIT_CONF_SELECT = 0 for 16 bit GPIF data bus.
  3. * Set CY_FX_MA_GPIF_16_32BIT_CONF_SELECT = 1 for 32 bit GPIF data bus.
  4. */ 
  5. #define CY_FX_GPIF_16_32BIT_CONF_SELECT (0) 

Also make sure that you select the Data Bus Width as 16 in the GPIF 2 Designer:

pastedImage_6.png

Regards,

Yashwant.

0 Likes
Reply
JaYe_3798301
New Contributor

Hi,

I tried to modify the clkDiv setting as suggested.

If the clkDiv value is larger than 36, the CyU3PGpifLoad function (line 16 in the following code snippet) would hang.

When the clkDiv value is less and equal to 36, the debug message in line 13 and 22 would printed out.

But when the clkDiv value is larger than 36, only the debug message in line 13 would be printed out.

Neither the debug message in line 19 nor line 22 printed out. So it could be hangs in the CyU3PGpifLoad  function call.

/* Initialize the p-port block. */

    pibClock.clkDiv = 32;

    pibClock.clkSrc = CY_U3P_SYS_CLK;

    pibClock.isHalfDiv = CyFalse;

    /* Disable DLL for sync GPIF */

    pibClock.isDllEnable = CyFalse;

    apiRetStatus = CyU3PPibInit(CyTrue, &pibClock);

    if (apiRetStatus != CY_U3P_SUCCESS)

    {

        CyU3PDebugPrint (4, "P-port Initialization failed, Error Code = %d\n",apiRetStatus);

        CyFxAppErrorHandler(apiRetStatus);

    }

    CyU3PDebugPrint (4, "P-port Initialization success\n");

    CyFxApplnSetPibDllParameters (CyTrue, 1, 0, 11);

    /* Load the GPIF configuration for Master mode. */

    apiRetStatus = CyU3PGpifLoad (&CyFxGpifConfig);

    if (apiRetStatus != CY_U3P_SUCCESS)

    {

        CyU3PDebugPrint (4, "CyU3PGpifLoad failed, Error Code = %d\n",apiRetStatus);

        CyFxAppErrorHandler(apiRetStatus);

    }

    CyU3PDebugPrint (4, "CyU3PGpifLoad success\n");

0 Likes
Reply
YashwantK_46
Moderator
Moderator

Hi Jay,

Can u please let us know the PCLK frequency (in MHz) that you want to use?

Regards,

Yashwant

0 Likes
Reply
JaYe_3798301
New Contributor

Hi,

I didn't change the clock setting in the AutoMaster example code.

Here's the code snippets

    CyU3PSysClockConfig_t clkCfg = {

    CyTrue,

    2, 2, 2,

    CyFalse,

    CY_U3P_SYS_CLK

    };

    /* Initialize the device */

    status = CyU3PDeviceInit (&clkCfg);

0 Likes
Reply
YashwantK_46
Moderator
Moderator

Hi Jay,

Please refer to KBA attached : Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733

The KBA refers to configuring the DLL block of FX3 (based on desired output PCLK).

The DLL block is configured in the firmware using CyFxApplnSetPibDllParameters(). The configuration is based on output PCLK desired which is mentioned in Table 2 of the above mentioned KBA.

The Output PCLK frequency is based on the pibClock.clkDiv parameter. If the value of clkDiv is 4 or 5 and if the clock_source is SYS_CLK, then Output PCLK >= 80MHz  and if value of clkDiv is greater than 5, Output PCLK < 80MHz and the values of the DLL parameters need to be updated accordingly from the table.

Please find the attached configuration shown in the images for PCLK<80MHz

Regards,

Yashwant

View solution in original post

0 Likes
Reply
JaYe_3798301
New Contributor

Hi,

Thanks for the tip of adjusting clock to <80Mhz.

Does the watermark value of the master and slave side of AN87216 need to be changed for 16-bit data bus?

I still cannot get a smooth data transmission as shown in the AN87216 application note with 16-bit data bus.

And I found in the forum that for AN65974 , the watermark value need to be changed for a 16-bit data bus.

So I wonder if it is also need to be chaged. If so, what's the value?

Thanks.

0 Likes
Reply
YashwantK_46
Moderator
Moderator

Hi Jay,

The watermark value basically defines the number of bytes of data that can be written/read after the watermark flag is asserted and changing the bus width from 32-bit to 16-bit only increases the number of bytes that can be written/read after the watermark flag is asserted which is not an issue.

Can you please share the timing diagram of GPIF interface where you observe the issue?

Also, can you tell about the direction of the direction of the data transfer (master to slave or vice-versa) ?

Regards,

Yashwant

0 Likes
Reply
JaYe_3798301
New Contributor

Hi,

Please find the attachment the master/salve transmission test result using the control center.

Also my master interface and slave GPIF interface and state machine.

Basically the only change I modified is change the data bus from 32bit to 16bit.

Then master -> slave seems to work fine.

But the slave -> to master doesn't acted as expected

0 Likes
Reply
YashwantK_46
Moderator
Moderator

Hi Jay,

I have tested the FX3 back-to-back configuration and implemented the slavefifo example but i was not able to find any issues with it.

The data was being transferred in the correct way.

As i have told earlier in the comment 7, you will have to change the DLL block parameters if the clkDiv value is more than 5 in order for the firmware to work.

Also, i have not made any changes to the watermark value in the firmware at all and it is as it was with the appnote.

Please check the connections and configure the dll parameters according to the PCLK frequency.

Regards,

Yashwant

0 Likes
Reply
JaYe_3798301
New Contributor

Hi Yashwant,

I have successfully get it working.

I follow your setting example, but keep these position definition as the original setting in the example.

#define CY_FX3_PIB_DLL_CORE_PHASE_POS   (4)                             /* Position of core clock phase field. */

#define CY_FX3_PIB_DLL_SYNC_PHASE_POS   (8)                             /* Position of sync clock phase field. */

#define CY_FX3_PIB_DLL_OP_PHASE_POS     (12)                            /* Position of output clock phase field. */

Thanks a lot for all your help.

Regards,

Jay

0 Likes
Reply