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USB Superspeed Peripherals

Anonymous
Not applicable

Hey Guys,

   

I have a Cypress FX 3 USB host connected to a Spartan 6 FPGA. I am using the GPIF 32bit interface to connect to it running in Synchronous mode.

   

I am running the interface at the maximum frequency of 100Mhz. 

   

I am not sure if i have got the timing constraints correct on the FPGA side.

   

I have drawn it out in the attached "GPIF Timing Diagram Mod". Basically this is what i think it should be, but i would like some confirmation from someone else that i am on the right track.

   

If there are additional constraints that you think i should add, please advise.

   

The timing constraints that I’ve specified in the UCF file is as follows:

   

##-------------------------  GPIF timing Constraints  -------------------------------##

   

# Offset constraints

   

# Timing group for pads

   

TIMEGRP "DQ" = PADS("DQ<0>") PADS("DQ<1>") PADS("DQ<2>") PADS("DQ<3>") PADS("DQ<4>") PADS("DQ<5>") PADS("DQ<6>") PADS("DQ<7>") PADS("DQ<8>") PADS("DQ<9>") PADS("DQ<10>") PADS("DQ<11>") PADS("DQ<12>") PADS("DQ<13>") PADS("DQ<14>") PADS("DQ<15>") PADS("DQ<16>") PADS("DQ<17>") PADS("DQ<18>") PADS("DQ<19>") PADS("DQ<20>") PADS("DQ<21>") PADS("DQ<22>") PADS("DQ<23>") PADS("DQ<24>") PADS("DQ<25>") PADS("DQ<26>") PADS("DQ<27>") PADS("DQ<28>") PADS("DQ<29>") PADS("DQ<30>") PADS("DQ<31>");

   

# Offset in (for Cypress FX3 -> FPGA)

   

TIMEGRP "DQ" OFFSET = IN 5ns VALID 7.5ns BEFORE "SYSCLK_P" RISING;

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3 Replies
Anonymous
Not applicable

I see that you have not mentioned what error do you see because of the timing mis-match. IT depends on the state machine. We have a reference.

   

We have a similar implementation where FX3 acts as a slave to a FPGA master. Please refer to AN65974 which is well tested and it includes the read/write timings for different scenario. You can build your application based on that.  Please go through the application note and the reference FX3+FPGA code:  http://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inter...

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Anonymous
Not applicable

form AN65974,Altera .sdc

   

create_clock -period 20 -name clk
create_clock -period 10 -name clk_100

   

set_output_delay -add_delay -rise -max -clock [get_clocks {clk_100}]  6.000 [get_ports {fdata*}]
set_output_delay -add_delay -rise -max -clock [get_clocks {clk_100}]  6.000 [get_ports {slwr}]
set_output_delay -add_delay -rise -max -clock [get_clocks {clk_100}]  6.000 [get_ports {pktend}]

   

There is no set_input_delay Constaints ​and Tco= max.8ns,There is almost one clk 10ns.How to set set_input_delay?

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New Contributor

I have a similar question about input delay, especially for the CTL signals.

In the timing specifications attached in the first message, you have tCTLO_max=8 ns and t_COH_min=0 ns.

This only gives us a window of 2 ns where we know that the CTL signal is stable...

How am I supposed to get my FPGA to comply with that together with the output delay?

I'm currently using the following, but can't get it to pass:

set_input_delay -clock { *FX3_PCLK } -min 0 [get_ports {FX3_CTL[0] FX3_CTL[4]}]

set_input_delay -clock { *FX3_PCLK } -max 8 [get_ports {FX3_CTL[0] FX3_CTL[4]}]

Has anyone else solved this?

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